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• Template
  [[Category:Computer Architecture]] [[Category:Acceleration and Transprecision]]
  4 KB (397 words) - 15:44, 14 February 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  ...electric polarization in the material by reorienting the crystal structure and aligning the electric dipoles in the direction of the electric field. ...ure in such a way that later studies will allow '''ML-based control of the system'''.
  6 KB (741 words) - 18:14, 21 July 2023
• Digitally-Controlled Analog Subtractive Sound Synthesis
  ..., etc. In recent years, building such music synthesizers became accessible and affordable as companies, e.g. Sound Semiconductor [1] or Coolaudio [2], man ...s) will first familiarize themselves with the ICs from Sound Semiconductor and then, manufacture a printed circuit board (PCB) that implements the subtrac
  5 KB (597 words) - 12:56, 4 December 2021
• Accelerator for Boosted Binary Features
  [[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]] Image feature extraction is an important analysis tool in many computer vision applications. In the context of this project, it is specifically use
  3 KB (373 words) - 11:51, 19 August 2017
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  ...ther fields. An interesting approach is that followed by the IBM TrueNorth architecture [Merolla14], an homogeneous fabric of 1 million digital spiking neurons tha ...ltra-low-power computing cluster composed of fully programmable RISC cores and traditional coprocessors/accelerators.
  5 KB (784 words) - 14:50, 30 November 2016
• Digital
  rect 0 910 1300 1820 [[Biomedical Circuits, Systems, and Applications]] rect 2600 0 3900 910 [[HW/SW Safety and Security]]
  7 KB (811 words) - 15:21, 23 February 2024
• High-speed Scene Labeling on FPGA
  ...h-speed implementations of synthetic vision systems capable of recognizing and classifying objects in a scene. Many popular algorithms in this area requir ...s much more applicable in industry and less constrained in terms of memory and interfaces. If desired by the student, also the use of high-level synthesis
  8 KB (1,197 words) - 18:18, 29 August 2016
• Improving our Smart Camera System
  ...s to process the acquired images faster based on the mostly static scenery and a second, multispectral camera module. ...mmunication capabilities to transmit suspicious cases to a remote computer and/or to add additional sensors (GPS, microphone). We would also like to port
  8 KB (1,176 words) - 16:26, 30 October 2020
• Design of a VLIW processor architecture based on RISC-V
  ...tructions), 48b, and 64b instructions. Our core is already supporting 16b, and 32b instructions, but as we have single-issue, in-order pipeline, the cores Moving to a very long instruction word (VLIW) architecture has several interesting advantages.
  3 KB (377 words) - 10:25, 5 November 2019
• Minimal Cost RISC-V core
  ...e currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also adde ...supports the basic instructions is enough. A very simple 2-3stage pipeline and minimal support for the number of registers can further decrease the power
  3 KB (384 words) - 17:24, 21 August 2019
• Fast Wakeup From Deep Sleep State
  [[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]] ...pplication areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.
  2 KB (236 words) - 08:35, 20 January 2021
• Design of a Fused Multiply Add Floating Point Unit
  ...''PULP''. Since it is a simple architecture, it consumes only little area and gives only little area savings when it is shared in a cluster. ...architecture for a fused multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.
  2 KB (346 words) - 10:26, 5 November 2019
• Open Power-On Chip Controller Study and Integration
  ...ed the Open-Power consortium, where a set of interested partners shares HW and SW IPs to create competitive computing node systems. ...on and firmware of the power 8 OCC allowing the implementation of advanced and custom-made power management features.
  3 KB (462 words) - 15:57, 9 September 2016
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...icularly on sensors that have a high need for extremely low power envelope and overall energy consumption, but at the same time can benefit from the avail ...ormation for us to recognize natural sounds, phonemes (and thus language), and music.
  9 KB (1,427 words) - 18:36, 5 September 2019
• Single-Bit-Synapse Spiking Neural System-on-Chip
  ...ther fields. An interesting approach is that followed by the IBM TrueNorth architecture [Merolla14], a homogeneous fabric of 1 million digital spiking neurons that ...his project we would like to develop a concrete proof of concept low power System-on-Chip where (small) practical applications such as Spiking Convolutional
  7 KB (1,000 words) - 12:22, 13 January 2017
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...high level semantically rich information out of raw data is deep learning, and in particular deep convolutional neural networks (CNNs). The task of infere ...design a PULP-based entire computation cluster around a set of deep, fast and low-power deep learning engines.
  6 KB (949 words) - 13:41, 10 November 2020
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  ...n than packed single-instruction multiple-data extensions (e.g. Intel AVX) and GPU-like single-instruction multiple-thread approaches to parallelism. ...-Riscy, one of the smallest RISC-V cores introduced at IIS [Schiavone2017] and use it as a baseline.
  6 KB (916 words) - 15:50, 7 December 2018
• Deep Learning for Brain-Computer Interface
  ...ever expanding applications suggesting its usage for a highly-accrue brain-computer interface. ...ct is to develop an algorithm based on deep learning for noninvasive brain-computer interfaces to classify EEG signals. The next step focuses on an efficient h
  3 KB (372 words) - 20:22, 1 April 2019
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
  ...in many fields, redefining the state of the art for computer vision, text and speech recognition, problem solving. Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art visual processing tasks.
  7 KB (1,001 words) - 10:43, 26 June 2017
• Trace Debugger for custom RISC-V Core
  ...f software development. It furthermore aids in bringing up silicon quickly and makes a software developer's life a lot easier. In smaller processors like ...ctual execution flow but break it into smaller pieces like halting the CPU and flushing certain data-structures.
  5 KB (729 words) - 11:27, 11 December 2018

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