Personal tools

Search results

From iis-projects

Jump to: navigation, search
  • * [[Analog| Analog and Mixed Signal Design]] * [[Digital| Digital Circuits and Systems]]
    5 KB (537 words) - 14:22, 23 February 2024
  • [[File:Ultra-low power processor design.jpg|thumb]] : 50% ASIC Design
    10 KB (1,669 words) - 18:01, 30 January 2014
  • : 40% ASIC Design * '''[[Design Review]]'''
    4 KB (397 words) - 14:44, 14 February 2023
  • ...rization and testing of piezoelectric polymers. It also aims to design the digital architecture in such a way that later studies will allow '''ML-based contro The development of a digital architecture that enables ML-based control of polarization and testing can
    6 KB (741 words) - 17:14, 21 July 2023
  • ...applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an ana ...finally measured during the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can b
    3 KB (382 words) - 19:00, 26 September 2017
  • [[File:Graestl.png|thumb|500px|Top: FPGA floorplan containing the microprocessor and the ing a separate AES/Grøstl design and GrÆStl.]]
    3 KB (434 words) - 11:01, 26 March 2015
  • ...(short for Musical Instrument Digital Interface) using a Raspberry Pi and digital-to-analog converters (DACs). The student(s) will first familiarize themselv : PCB design experience
    5 KB (597 words) - 11:56, 4 December 2021
  • : 70% Hw Architecture & ASIC Implementation * '''[[Design Review]]'''
    3 KB (366 words) - 11:40, 1 June 2017
  • ...([[Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment]]), : 40% Hw Architecture & FPGA Implementation
    3 KB (373 words) - 10:51, 19 August 2017
  • * Digital design * Digital signal processing
    2 KB (336 words) - 16:27, 1 November 2017
  • ...IBM TrueNorth architecture [Merolla14], an homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification at a very low po Tight integration of digital spiking neurons with other kinds of low-power computers is a totally unexpl
    5 KB (784 words) - 13:50, 30 November 2016
  • ...throughputs of 100Gbit/s and even more, either as an ASIC or as part of an FPGA project. You will compare your personal results with previous work from oth * Attend VLSI II (for ASIC designs)
    2 KB (317 words) - 12:13, 14 April 2016
  • The goal of this project is to implement the digital baseband of a Bluetooth LE receiver, that is able to gather information abo : 50% Hardware design (HLS or VHDL)
    3 KB (449 words) - 11:12, 4 November 2019
  • ...IC with only this block, or integrate it into our RF SoC and test it on an FPGA. : 40% Hardware Design (HLS/VHDL)
    3 KB (345 words) - 09:52, 5 April 2022
  • : 40% ASIC Design * '''[[Design Review]]'''
    3 KB (456 words) - 07:35, 20 January 2021
  • ...table 3D ultrasound systems, new algorithms and hardware architectures for digital beamforming are currently being developed at IIS. ...feasibility study of the complete beamformer architecture, the fabricated ASIC is tested, measured and physically characterized in a second phase.
    3 KB (423 words) - 10:23, 10 November 2017
  • ...ill involve modeling in Matlab but mostly it is HDL design, synthesis, and FPGA testing. This project is a perfect opportunity to apply architectural design methods. The outcome is likely to be the first EC-GSM capable transmitter i
    3 KB (384 words) - 15:41, 17 July 2016
  • ...a hardware description language (HDL) and deploy it to the LTE transceiver FPGA board. : 50% FPGA Design
    3 KB (335 words) - 13:20, 4 November 2019
  • # The power dissipation of a digital circuit is proportional to the squared supply voltage. Reducing it to the l ...ion should also serve as evaluation platform for a later mixed-signal ASIC design.
    3 KB (438 words) - 17:06, 3 February 2015
  • [[Category:Digital]] [[Category:Software]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Digital]] [[Category:System Design]]
    5 KB (707 words) - 10:22, 5 February 2016

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)