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• Ultra-low power processor design
  ...hitecture. We will use a state of the art 28nm SOI process to evaluate the performance of the processor. ====Energy Efficient Computing using Multicore Systems====
  10 KB (1,669 words) - 19:01, 30 January 2014
• Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  ...P TD-HSPA wireless communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect ...the future requires a paradigm shift from the assumption of 100% reliable computing to fault-tolerant
  2 KB (343 words) - 13:56, 9 February 2015
• Digital
  rect 0 0 1300 910 [[High Performance SoCs]] * '''[[High Performance SoCs]]'''
  7 KB (811 words) - 15:21, 23 February 2024
• Acceleration and Transprecision
  ...ccelerators are not limited to high performance sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be per
  2 KB (275 words) - 17:05, 24 November 2023
• Ultra-Efficient Visual Classification on Movidius Myriad2
  ...f 12 SHAVE processors, that leverage VLIW and SIMD operations to achieve a high level of energy efficiency. The SHAVE processors share a 2MB tightly couple # Measurement of performance and energy efficiency of the proposed solution
  4 KB (593 words) - 14:57, 30 November 2016
• Covariant Feature Detector on Parallel Ultra Low Power Architecture
  The development of a CV library featuring high level capabilities is key tackling real word problems such as wearable devi ...to operate on a large range of operating voltages, achieving in this way a high level of energy efficiency over a wide range of application workloads.
  4 KB (628 words) - 16:16, 20 February 2018
• FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  ...s able to perform accurate tomographic reconstruction of SoS/AA, providing high-contrast tumor images. In the next months, this technology will be evaluate ...creening procedure in medical trials, we now aim at incorporating portable computing platforms as an add-on to conventional ultrasound systems. This platforms w
  3 KB (411 words) - 14:07, 30 August 2017
• A Wireless Sensor Network for HPC monitoring
  ...ed by wireless links. We want to apply this scenario to a High Performance Computing (HPC) infrastructure for environmental monitoring, aiming at an improving o ...cation (simulations), measuring power-consumption, and assessing detection performance in lab. conditions
  5 KB (617 words) - 16:22, 27 February 2018
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr ...en-source ARM-Linux loss-less implementations when available) for the best performance on our application-scenario.
  3 KB (351 words) - 16:19, 27 February 2018
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr
  3 KB (394 words) - 16:19, 27 February 2018
• Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr ...d at the node power-supply. Such routing-board will integrate a high-speed high-resolution ADC, which will be controlled by the built-in Programmable Real-
  3 KB (440 words) - 16:15, 1 September 2017
• Open Power-On Chip Controller Study and Integration
  ...re a set of interested partners shares HW and SW IPs to create competitive computing node systems. The power8 CPUs features an interesting power management design where the computing cores are coupled with a dedicated PPC 405 hard real-time core, which imple
  3 KB (462 words) - 15:57, 9 September 2016
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. Optimizing for energy efficiency requires m ...ce with external monitors and not with the internal per-core architectural performance counters.
  3 KB (417 words) - 15:55, 9 September 2016
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...at the same time can benefit from the availability of a level of computing performance orders of magnitude better than that of ultra-low power microcontrollers. * [Cassidy13] A. S. Cassidy et al., “Cognitive computing building block: A versatile and efficient digital neuron model for neurosyn
  9 KB (1,427 words) - 18:36, 5 September 2019
• Deep Learning Projects
  ...rties make DNNs an ideal fit for modern SIMD architectures and distributed computing systems. ...each data sample. Hence, to reduce the pressure of DNNs on the underlying computing infrastructure, research in computational deep learning has focussed on two
  18 KB (2,473 words) - 19:29, 19 February 2024
• BigPULP: Multicluster Synchronization Extensions
  ...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
  6 KB (801 words) - 15:05, 23 August 2018
• Neural Networks Framwork for Embedded Plattforms
  ...ly trained reduced-precision networks reach similar performance than their high-precision equivalents. In previous projects, we have successfully developed ...-based special-purpose instructions on the PULP platform to accelerate the computing task.
  3 KB (317 words) - 14:40, 14 April 2021
• HERO: TLB Invalidation
  ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t ...ous Embedded SoCs", ''ESWEEK special issue of ACM Transactions on Embedded Computing Systems'' [https://dl.acm.org/citation.cfm?id=3126560 link]
  6 KB (796 words) - 17:19, 18 November 2019
• Heterogeneous SoCs
  ...terogeneous integration has allowed (not only) Apple to get high computing performance under tight power constraints.]] ...Heterogeneous systems on chip''' are currently one of the main drivers for performance-per-energy advancements in various application domains.
  3 KB (421 words) - 18:41, 28 October 2020

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