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• Ultra-low power processor design
  ...ionality which will never be used in the target system and it is therefore not necessary to maintain all this functionality. Removing caches, IMMU, DMMU, ..., at least one processor will have to wait(stall) until the memory becomes available. To simulate such a miss in a single core structure, an acknowledge will be
  10 KB (1,669 words) - 19:01, 30 January 2014
• Final Report
  ...a problem, it means that solutions offered in ''related work'' were simply not good enough. Explain what is missing in the related work, and lead into you * Introduction (and Conclusion) are more easy to finish last, do not get stuck at the beginning trying to write a good introduction.
  4 KB (618 words) - 10:22, 10 March 2016
• Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  ...ime with the same naturalness as the iconic stethoscope. These new systems not only enable new diagnostic possibilities, but also push the limits of the t [[Category:Available]]
  4 KB (614 words) - 20:10, 17 February 2015
• Flexible Electronic Systems and Embedded Epidermal Devices
  ...pment''' of such systems faces a '''number of challenges'''. These include not only material properties per se (e.g., flexibility, stretchability, or bioc ===Available Projects===
  4 KB (444 words) - 12:43, 23 July 2023
• Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
  is not feasible due to prohibitive complexity. This is due to the fact that the co
  5 KB (684 words) - 10:43, 6 November 2017
• Weekly Reports
  Please use ASCII text, if needed with embedded figures. Do not send your report as pdf or .docx in attachment. This prevents Prof. Benini * Address your mail to Prof. Benini, do not forget to add your supervisors in CC
  7 KB (1,133 words) - 07:08, 7 October 2023
• Power Optimization in Multipliers
  ...th little hardware overhead and speed penalty. Such techniques however are not compatible with standard-cell technologies. The goal of this project is to [[Category:Available]]
  3 KB (386 words) - 16:23, 30 October 2020
• Low-power chip-to-chip communication network
  ...aller chips (like the ones relevant for our research) as there are usually not enough number of I/O pins to take advantage of parallelization. Most soluti ===Status: Available ===
  3 KB (492 words) - 12:34, 7 November 2017
• Hardware Accelerated Derivative Pricing
  students who have broad interests, not just in hardware, but also in ===Status: Available ===
  3 KB (429 words) - 09:42, 12 October 2017
• Harald Kröll
  ==Available Projects== category = Available
  764 bytes (92 words) - 17:27, 1 November 2017
• CPS Software-Configurable State-Machine
  To save power, this unit will not be a conventional fully synchronously clocked design: the configurable stat ===Status: Available ===
  3 KB (418 words) - 11:24, 10 November 2017
• Successive Interference Cancellation for 3G Downlink
  ...stems, (optimum) joint maximum-likelihood sequence detection is in general not feasible. Instead, power- and area-efficient linear algorithms, such as lin
  2 KB (330 words) - 18:59, 10 February 2015
• Ab-initio Simulation of Strained Thermoelectric Materials
  ===Status: Available === ...ructure calculations and the Boltzmann Transport Equation appreciated, but not required
  3 KB (456 words) - 15:43, 4 September 2019
• Implementation of a 2-D model for Li-ion batteries
  ...ar and wind power will become true alternatives to fossil fuels if they do not need to be consumed instantaneously, but can be stored first and then used ...mid 90's, are computationally very efficient to fulfill this task, but do not capture the shape of the electrode active components. The goal of this proj
  3 KB (431 words) - 15:41, 4 September 2019
• Design and Implementation of an Approximate Floating Point Unit
  ...gy efficient implementation because ''floating point'' (FP)-operations are not always used which means they remain idle for lots of cycles. Sharing FPUs
  3 KB (377 words) - 10:58, 21 February 2018
• A Multiview Synthesis Core in 65 nm CMOS
  ...cement of image pixels allowed to design a hardware architecture that does not require an off-chip memory. The complexity of the chip is 6.75 MGE (includi [[Category:Available]]
  4 KB (524 words) - 15:49, 13 May 2015
• Compressed Sensing Reconstruction on FPGA
  ...he OMP (bottom) hardware architecture utilizing the multipliers (VMU unit) available on today’s FPGA platforms.]] ...ly for applications with real-time requirements, software realizations are not fast enough. We therefore implemented generic high- speed FPGA implementati
  3 KB (389 words) - 18:56, 28 January 2014
• Pirmin Vogel
  ...19, he joined [https://www.lowrisc.org lowRISC C.I.C.], a Cambridge-based, not-for-profit company using collaborative engineering to develop and maintain ==Available Projects==
  1 KB (193 words) - 15:39, 3 March 2020
• Multi-Band Receiver Design for LTE Mobile Communication
  ...are becoming more and more important in our daily life. A mobile phone is not primarily a wireless phone anymore. It is rather a lifestyle device connec
  2 KB (275 words) - 17:47, 29 January 2014
• High Performance Cellular Receivers in Very Advanced CMOS
  ...frequency range. Using one input pin for every frecuency band to cover is not feasible for a transceiver that operates on latest cellular communication s
  2 KB (275 words) - 13:02, 10 March 2015

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