Short pages
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Showing below up to 20 results in range #1 to #20.
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- (hist) Deconvolution Accelerator for On-Chip Semi-Supervised Learning [0 bytes]
- (hist) Neural Processing [0 bytes]
- (hist) Near-Memory Training of Neural Networks [0 bytes]
- (hist) Biomedical System on Chips [0 bytes]
- (hist) Mattia [0 bytes]
- (hist) Enabling Standalone Operation [0 bytes]
- (hist) Optimal System Duty Cycling [0 bytes]
- (hist) Implementation of a Heterogeneous System for Image Processing on an FPGA [0 bytes]
- (hist) Palm size chip NMR [0 bytes]
- (hist) A Snitch-based Compute Accelerator for HERO [0 bytes]
- (hist) (M): A Flexible Peripheral System for High-Performance Systems on Chip [0 bytes]
- (hist) IBM Research–Zurich [0 bytes]
- (hist) DaCe on Snitch [0 bytes]
- (hist) SSR combined with FREP in LLVM/Clang [0 bytes]
- (hist) IBM A2O Core [0 bytes]
- (hist) IP-Based SoC Generation and Configuration (1-3S) [0 bytes]
- (hist) MemPool on HERO [0 bytes]
- (hist) ISA extensions in the Snitch Processor for Signal Processing (1M) [0 bytes]
- (hist) Integrating Hardware Accelerators into Snitch [0 bytes]
- (hist) Prasadar [0 bytes]