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Showing below up to 500 results in range #1 to #500.

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1. (hist) ‎Deconvolution Accelerator for On-Chip Semi-Supervised Learning ‎[0 bytes]
2. (hist) ‎Neural Processing ‎[0 bytes]
3. (hist) ‎Near-Memory Training of Neural Networks ‎[0 bytes]
4. (hist) ‎Biomedical System on Chips ‎[0 bytes]
5. (hist) ‎Mattia ‎[0 bytes]
6. (hist) ‎Enabling Standalone Operation ‎[0 bytes]
7. (hist) ‎Optimal System Duty Cycling ‎[0 bytes]
8. (hist) ‎Implementation of a Heterogeneous System for Image Processing on an FPGA ‎[0 bytes]
9. (hist) ‎Palm size chip NMR ‎[0 bytes]
10. (hist) ‎A Snitch-based Compute Accelerator for HERO ‎[0 bytes]
11. (hist) ‎(M): A Flexible Peripheral System for High-Performance Systems on Chip ‎[0 bytes]
12. (hist) ‎IBM Research–Zurich ‎[0 bytes]
13. (hist) ‎DaCe on Snitch ‎[0 bytes]
14. (hist) ‎SSR combined with FREP in LLVM/Clang ‎[0 bytes]
15. (hist) ‎IBM A2O Core ‎[0 bytes]
16. (hist) ‎IP-Based SoC Generation and Configuration (1-3S) ‎[0 bytes]
17. (hist) ‎MemPool on HERO ‎[0 bytes]
18. (hist) ‎ISA extensions in the Snitch Processor for Signal Processing (1M) ‎[0 bytes]
19. (hist) ‎Integrating Hardware Accelerators into Snitch ‎[0 bytes]
20. (hist) ‎Prasadar ‎[0 bytes]
21. (hist) ‎On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks ‎[0 bytes]
22. (hist) ‎Test project ‎[0 bytes]
23. (hist) ‎Benchmarking a heterogeneous 217-core MPSoC on HPC applications ‎[0 bytes]
24. (hist) ‎Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) ‎[0 bytes]
25. (hist) ‎A Post-Simulation Trace-Based RISC-V GDB Debugging Server ‎[0 bytes]
26. (hist) ‎Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) ‎[0 bytes]
27. (hist) ‎Versatile HW SW Digital PHY for inter chip communication ‎[0 bytes]
28. (hist) ‎Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) ‎[0 bytes]
29. (hist) ‎Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) ‎[0 bytes]
30. (hist) ‎Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) ‎[0 bytes]
31. (hist) ‎Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) ‎[0 bytes]
32. (hist) ‎Test page ‎[16 bytes]
33. (hist) ‎A Trustworthy Three-Factor Authentication System ‎[40 bytes]
34. (hist) ‎Influence of the Initial FilamentGeometry on the Forming Step in CBRAM ‎[75 bytes]
35. (hist) ‎Theory, Algorithms, and Hardware for Beyond 5G ‎[120 bytes]
36. (hist) ‎Positioning with Wireless Signals ‎[121 bytes]
37. (hist) ‎All-Digital In-Memory Processing ‎[121 bytes]
38. (hist) ‎Real-Time Optimization ‎[121 bytes]
39. (hist) ‎Audio Signal Processing ‎[123 bytes]
40. (hist) ‎Simultaneous Sensing and Communication ‎[123 bytes]
41. (hist) ‎Mixed-Signal Circuit Design ‎[123 bytes]
42. (hist) ‎Analog IC Design ‎[130 bytes]
43. (hist) ‎Mixed Signal IC Design ‎[136 bytes]
44. (hist) ‎AnalogInt ‎[343 bytes]
45. (hist) ‎Atretter ‎[362 bytes]
46. (hist) ‎Tbenz ‎[362 bytes]
47. (hist) ‎Audio ‎[403 bytes]
48. (hist) ‎Taimir Aguacil ‎[416 bytes]
49. (hist) ‎Christoph Keller ‎[423 bytes]
50. (hist) ‎Project Meetings ‎[425 bytes]
51. (hist) ‎Project Plan ‎[453 bytes]
52. (hist) ‎Moritz Schneider ‎[459 bytes]
53. (hist) ‎Software ‎[473 bytes]
54. (hist) ‎Stefan Lippuner ‎[532 bytes]
55. (hist) ‎Benjamin Sporrer ‎[567 bytes]
56. (hist) ‎Philipp Schönle ‎[569 bytes]
57. (hist) ‎Design Review ‎[577 bytes]
58. (hist) ‎Nils Wistoff ‎[578 bytes]
59. (hist) ‎Mauro Salomon ‎[637 bytes]
60. (hist) ‎Cryptography ‎[645 bytes]
61. (hist) ‎Libria ‎[646 bytes]
62. (hist) ‎Karim Badawi ‎[653 bytes]
63. (hist) ‎Matthias Korb ‎[698 bytes]
64. (hist) ‎Energy Efficient Circuits and IoT Systems Group ‎[736 bytes]
65. (hist) ‎EECIS ‎[740 bytes]
66. (hist) ‎Harald Kröll ‎[764 bytes]
67. (hist) ‎Pascal Hager ‎[775 bytes]
68. (hist) ‎Research ‎[789 bytes]
69. (hist) ‎Ultrasound ‎[797 bytes]
70. (hist) ‎Federico Villani ‎[834 bytes]
71. (hist) ‎Coding Guidelines ‎[841 bytes]
72. (hist) ‎Herschmi ‎[859 bytes]
73. (hist) ‎Matheus Cavalcante ‎[890 bytes]
74. (hist) ‎Telecommunications ‎[892 bytes]
75. (hist) ‎Benjamin Weber ‎[894 bytes]
76. (hist) ‎Norbert Felber ‎[897 bytes]
77. (hist) ‎Christoph Leitner ‎[928 bytes]
78. (hist) ‎Robert Balas ‎[931 bytes]
79. (hist) ‎GRAND Hardware Implementation ‎[990 bytes]
80. (hist) ‎FPGA ‎[1,020 bytes]
81. (hist) ‎Matteo Perotti ‎[1,028 bytes]
82. (hist) ‎Andreas Kurth ‎[1,029 bytes]
83. (hist) ‎Fabian Schuiki ‎[1,031 bytes]
84. (hist) ‎Stefan Mach ‎[1,044 bytes]
85. (hist) ‎Eye tracking ‎[1,058 bytes]
86. (hist) ‎Integrated Devices, Electronics, And Systems ‎[1,058 bytes]
87. (hist) ‎Frank K. Gürkaynak ‎[1,072 bytes]
88. (hist) ‎Low-Power Time Synchronization for IoT Applications ‎[1,085 bytes]
89. (hist) ‎Physical Layer Implementation of HSPA+ 4G Mobile Transceiver ‎[1,088 bytes]
90. (hist) ‎Guillaume Mocquard ‎[1,117 bytes]
91. (hist) ‎Final Presentation ‎[1,130 bytes]
92. (hist) ‎Channel Estimation for 3GPP TD-SCDMA ‎[1,144 bytes]
93. (hist) ‎Synchronization and Power Control Concepts for 3GPP TD-SCDMA ‎[1,145 bytes]
94. (hist) ‎Michael Muehlberghuber ‎[1,160 bytes]
95. (hist) ‎An FPGA-Based Testbed for 3G Mobile Communications Receivers ‎[1,168 bytes]
96. (hist) ‎FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications ‎[1,194 bytes]
97. (hist) ‎Michael Rogenmoser ‎[1,211 bytes]
98. (hist) ‎Interference Cancellation for EC-GSM-IoT ‎[1,281 bytes]
99. (hist) ‎Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) ‎[1,284 bytes]
100. (hist) ‎ASIC ‎[1,286 bytes]
101. (hist) ‎PREM on PULP ‎[1,304 bytes]
102. (hist) ‎Configurable Ultra Low Power LDO ‎[1,306 bytes]
103. (hist) ‎Exploring Algorithms for Early Seizure Detection ‎[1,329 bytes]
104. (hist) ‎SW/HW Predictability and Security ‎[1,333 bytes]
105. (hist) ‎Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) ‎[1,378 bytes]
106. (hist) ‎Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) ‎[1,408 bytes]
107. (hist) ‎Design of low mismatch DAC used for VAD ‎[1,409 bytes]
108. (hist) ‎Scan Chain Fault Injection in a PULP SoC (1S) ‎[1,421 bytes]
109. (hist) ‎Receiver design for the DigRF 4G high speed serial link ‎[1,431 bytes]
110. (hist) ‎Beat Cadence ‎[1,442 bytes]
111. (hist) ‎Precise Ultra-low-power Timer ‎[1,446 bytes]
112. (hist) ‎Digital Audio Processor for Cellular Applications ‎[1,448 bytes]
113. (hist) ‎Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) ‎[1,466 bytes]
114. (hist) ‎Multiuser Equalization and Detection for 3GPP TD-SCDMA ‎[1,484 bytes]
115. (hist) ‎Creating A Boundry Scan Generator (1-3S/B/2-3G) ‎[1,488 bytes]
116. (hist) ‎Design of a D-Band Variable Gain Amplifier for 6G Communication ‎[1,522 bytes]
117. (hist) ‎Positioning for the cellular Internet of Things ‎[1,525 bytes]
118. (hist) ‎ASIC Design of a Gaussian Message Passing Processor ‎[1,526 bytes]
119. (hist) ‎Pirmin Vogel ‎[1,528 bytes]
120. (hist) ‎Novel Metastability Mitigation Technique ‎[1,561 bytes]
121. (hist) ‎High resolution, low power Sigma Delta ADC ‎[1,568 bytes]
122. (hist) ‎Marco Bertuletti ‎[1,571 bytes]
123. (hist) ‎Hardware Accelerator Integration into Embedded Linux ‎[1,578 bytes]
124. (hist) ‎LightProbe - CNN-Based-Image-Reconstruction ‎[1,582 bytes]
125. (hist) ‎Hardware Support for IDE in Multicore Environment ‎[1,591 bytes]
126. (hist) ‎Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) ‎[1,597 bytes]
127. (hist) ‎Ultrasound signal processing acceleration with CUDA ‎[1,600 bytes]
128. (hist) ‎Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) ‎[1,645 bytes]
129. (hist) ‎Synchronisation and Cyclic Prefix Handling For LTE Testbed ‎[1,649 bytes]
130. (hist) ‎Audio Video Preprocessing In Parallel Ultra Low Power Platform ‎[1,650 bytes]
131. (hist) ‎Fast Wakeup From Deep Sleep State ‎[1,665 bytes]
132. (hist) ‎Fault Tolerance ‎[1,665 bytes]
133. (hist) ‎EvaLTE: A 2G/3G/4G Cellular Transceiver FMC ‎[1,679 bytes]
134. (hist) ‎Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) ‎[1,705 bytes]
135. (hist) ‎GSM Voice Capacity Evolution - VAMOS ‎[1,707 bytes]
136. (hist) ‎Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) ‎[1,722 bytes]
137. (hist) ‎Design and Implementation of a multi-mode multi-master I2C peripheral ‎[1,729 bytes]
138. (hist) ‎Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) ‎[1,729 bytes]
139. (hist) ‎System Analysis and VLSI Design of NB-IoT Baseband Processing ‎[1,736 bytes]
140. (hist) ‎Toward Superposition of Brain-Computer Interface Models ‎[1,758 bytes]
141. (hist) ‎State-Saving @ NXP ‎[1,767 bytes]
142. (hist) ‎Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) ‎[1,776 bytes]
143. (hist) ‎Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) ‎[1,794 bytes]
144. (hist) ‎Power Saver Mode for Cellular Internet of Things Receivers ‎[1,795 bytes]
145. (hist) ‎Bluetooth Low Energy receiver in 65nm CMOS ‎[1,795 bytes]
146. (hist) ‎Adding Linux Support to our DMA Engine (1-2S/B) ‎[1,795 bytes]
147. (hist) ‎LTE-Advanced RF Front-end Design in 28nm CMOS Technology ‎[1,811 bytes]
148. (hist) ‎5G Cellular RF Front-end Design in 22nm CMOS Technology ‎[1,818 bytes]
149. (hist) ‎AXI-based Network on Chip (NoC) system ‎[1,825 bytes]
150. (hist) ‎Energy Efficient Serial Link ‎[1,833 bytes]
151. (hist) ‎LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) ‎[1,841 bytes]
152. (hist) ‎Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets ‎[1,852 bytes]
153. (hist) ‎Open Source Baseband Firmware for 2G Cellular Networks ‎[1,858 bytes]
154. (hist) ‎Interference Cancellation for the cellular Internet of Things ‎[1,860 bytes]
155. (hist) ‎Bluetooth Low Energy network with optimized data throughput ‎[1,860 bytes]
156. (hist) ‎Ultrasound Low power WiFi with IMX7 ‎[1,861 bytes]
157. (hist) ‎Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets ‎[1,863 bytes]
158. (hist) ‎Fast and Accurate Multiclass Inference for Brain–Computer Interfaces ‎[1,865 bytes]
159. (hist) ‎Low-Dropout Regulators for Magnetic Resonance Imaging ‎[1,867 bytes]
160. (hist) ‎Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) ‎[1,878 bytes]
161. (hist) ‎Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf ‎[1,896 bytes]
162. (hist) ‎Implementation of a Coherent Application-Class Multicore System (1-2S) ‎[1,897 bytes]
163. (hist) ‎Multi-Band Receiver Design for LTE Mobile Communication ‎[1,907 bytes]
164. (hist) ‎LightProbe ‎[1,907 bytes]
165. (hist) ‎Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA ‎[1,914 bytes]
166. (hist) ‎Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) ‎[1,929 bytes]
167. (hist) ‎Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen ‎[1,931 bytes]
168. (hist) ‎Enabling Standalone Operation for a Mobile Health Platform ‎[1,934 bytes]
169. (hist) ‎Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC ‎[1,946 bytes]
170. (hist) ‎GUI-developement for an action-cam-based eye tracking device ‎[1,949 bytes]
171. (hist) ‎High Performance Cellular Receivers in Very Advanced CMOS ‎[1,952 bytes]
172. (hist) ‎Make Cellular Internet of Things Receivers Smart ‎[1,954 bytes]
173. (hist) ‎Towards Formal Verification of the iDMA Engine (1-3S/B) ‎[1,954 bytes]
174. (hist) ‎Non-binary LDPC Decoder for Deep-Space Optical Communications ‎[1,958 bytes]
175. (hist) ‎Jammer-Resilient Synchronization for Wireless Communications ‎[1,962 bytes]
176. (hist) ‎Wireless Biomedical Signal Acquisition Device ‎[1,982 bytes]
177. (hist) ‎3D Ultrasound Bubble Tracking ‎[1,982 bytes]
178. (hist) ‎RazorEDGE: An Evolved EDGE DBB ASIC ‎[1,995 bytes]
179. (hist) ‎Implementation of a Cache Reliability Mechanism (1S/M) ‎[1,996 bytes]
180. (hist) ‎ASIC Design of a Sigma Point Processor ‎[1,998 bytes]
181. (hist) ‎Beat DigRF ‎[2,000 bytes]
182. (hist) ‎Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening ‎[2,001 bytes]
183. (hist) ‎Energy Efficient AXI Interface to Serial Link Physical Layer ‎[2,020 bytes]
184. (hist) ‎High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS ‎[2,024 bytes]
185. (hist) ‎Signal to Noise Ratio Estimation for 3G standards ‎[2,025 bytes]
186. (hist) ‎Channel Estimation for TD-HSPA ‎[2,028 bytes]
187. (hist) ‎Event-Driven Computing ‎[2,043 bytes]
188. (hist) ‎Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC ‎[2,044 bytes]
189. (hist) ‎Acceleration and Transprecision ‎[2,054 bytes]
190. (hist) ‎Implementation of an AES Hardware Processing Engine (B/S) ‎[2,064 bytes]
191. (hist) ‎Analog building blocks for mmWave manipulation ‎[2,064 bytes]
192. (hist) ‎Intelligent Power Management Unit (iPMU) ‎[2,067 bytes]
193. (hist) ‎Compression of Ultrasound data on FPGA ‎[2,067 bytes]
194. (hist) ‎Predictable Execution ‎[2,068 bytes]
195. (hist) ‎Machine Learning on Ultrasound Images ‎[2,071 bytes]
196. (hist) ‎Design of a Digital Audio Module for Ultra-Low Power Cellular Applications ‎[2,072 bytes]
197. (hist) ‎Improving Resiliency of Hyperdimensional Computing ‎[2,073 bytes]
198. (hist) ‎Audio DAC Conversion Jitter Measurement System ‎[2,075 bytes]
199. (hist) ‎Sub Noise Floor Channel Estimation for the Cellular Internet of Things ‎[2,078 bytes]
200. (hist) ‎Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) ‎[2,089 bytes]
201. (hist) ‎ASIC Design Projects ‎[2,094 bytes]
202. (hist) ‎Fault-Tolerant Floating-Point Units (M) ‎[2,097 bytes]
203. (hist) ‎Internet of Things SoC Characterization ‎[2,109 bytes]
204. (hist) ‎SHAre - An application Specific Instruction Set Processor for SHA-2/3 ‎[2,124 bytes]
205. (hist) ‎A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance ‎[2,129 bytes]
206. (hist) ‎DC-DC Buck converter in 65nm CMOS ‎[2,131 bytes]
207. (hist) ‎A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications ‎[2,135 bytes]
208. (hist) ‎Design of a Prototype Chip with Interleaved Memory and Network-on-Chip ‎[2,152 bytes]
209. (hist) ‎EvalEDGE: A 2G Cellular Transceiver FMC ‎[2,158 bytes]
210. (hist) ‎High Throughput Turbo Decoder Design ‎[2,163 bytes]
211. (hist) ‎Machine Learning for extracting Muscle features using Ultrasound ‎[2,167 bytes]
212. (hist) ‎Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) ‎[2,176 bytes]
213. (hist) ‎Development of an efficient algorithm for quantum transport codes ‎[2,177 bytes]
214. (hist) ‎Extension and Evaluation of TinyDMA (1-2S/B/2-3G) ‎[2,186 bytes]
215. (hist) ‎Hardware Exploration of Shared-Exponent MiniFloats (M) ‎[2,189 bytes]
216. (hist) ‎Low Power Embedded Systems ‎[2,192 bytes]
217. (hist) ‎Self Aware Epilepsy Monitoring ‎[2,194 bytes]
218. (hist) ‎An Ultra-Low-Power Neuromorphic Spiking Neuron Design ‎[2,197 bytes]
219. (hist) ‎An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications ‎[2,200 bytes]
220. (hist) ‎LightProbe - Ultracompact Power Supply PCB ‎[2,201 bytes]
221. (hist) ‎Taping a Safer Silicon Implementation of Snitch (M/2-3S) ‎[2,217 bytes]
222. (hist) ‎LAPACK/BLAS for FPGA ‎[2,219 bytes]
223. (hist) ‎Extending the RISCV backend of LLVM to support PULP Extensions ‎[2,219 bytes]
224. (hist) ‎Android Software Design ‎[2,224 bytes]
225. (hist) ‎Reconfigurability of SHA-3 candidates ‎[2,230 bytes]
226. (hist) ‎Flexible Front-End Circuit for Biomedical Data Acquisition ‎[2,232 bytes]
227. (hist) ‎Learning Image Decompression with Convolutional Networks ‎[2,236 bytes]
228. (hist) ‎Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC ‎[2,237 bytes]
229. (hist) ‎Development of a syringe label reader for the neurocritical care unit ‎[2,242 bytes]
230. (hist) ‎Machine Learning for extracting Muscle features using Ultrasound 2 ‎[2,257 bytes]
231. (hist) ‎Low Power Embedded Systems and Wireless Sensors Networks ‎[2,258 bytes]
232. (hist) ‎PREM Runtime Scheduling Policies ‎[2,259 bytes]
233. (hist) ‎Triple-Core PULPissimo ‎[2,260 bytes]
234. (hist) ‎Energy Neutral Multi Sensors Wearable Device ‎[2,264 bytes]
235. (hist) ‎Channel Decoding for TD-HSPA ‎[2,272 bytes]
236. (hist) ‎RISC-V base ISA for ultra-low-area cores (2-3G) ‎[2,276 bytes]
237. (hist) ‎David J. Mack ‎[2,280 bytes]
238. (hist) ‎Real-time eye movement analysis on a tablet computer ‎[2,281 bytes]
239. (hist) ‎Baseband Processor Development for 4G IoT ‎[2,283 bytes]
240. (hist) ‎Low-power Temperature-insensitive Timer ‎[2,284 bytes]
241. (hist) ‎Super Resolution Radar/Imaging at mm-Wave frequencies ‎[2,285 bytes]
242. (hist) ‎LightProbe - WIFI extension (PCB) ‎[2,299 bytes]
243. (hist) ‎Running Rust on PULP ‎[2,302 bytes]
244. (hist) ‎Simulation of 2D artificial cilia metasurface in COMSOL ‎[2,307 bytes]
245. (hist) ‎Turbo Decoder Design for High Code Rates ‎[2,309 bytes]
246. (hist) ‎Visualizing Functional Microbubbles using Ultrasound Imaging ‎[2,317 bytes]
247. (hist) ‎Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials ‎[2,318 bytes]
248. (hist) ‎TCNs vs. LSTMs for Embedded Platforms ‎[2,318 bytes]
249. (hist) ‎WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing ‎[2,319 bytes]
250. (hist) ‎Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) ‎[2,332 bytes]
251. (hist) ‎Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) ‎[2,341 bytes]
252. (hist) ‎Design and Implementation of ultra low power vision system ‎[2,342 bytes]
253. (hist) ‎Ultra-low power transceiver for implantable devices ‎[2,353 bytes]
254. (hist) ‎Biomedical Systems on Chip ‎[2,360 bytes]
255. (hist) ‎Machine Learning for extracting Muscle features from Ultrasound raw data ‎[2,364 bytes]
256. (hist) ‎Time Gain Compensation for Ultrasound Imaging ‎[2,365 bytes]
257. (hist) ‎Digital Control of a DC/DC Buck Converter ‎[2,369 bytes]
258. (hist) ‎Ultrasound image data recycler ‎[2,373 bytes]
259. (hist) ‎Design of State Retentive Flip-Flops ‎[2,374 bytes]
260. (hist) ‎Successive Approximation Register (SAR) ADC ‎[2,376 bytes]
261. (hist) ‎Compressed Sensing vs JPEG ‎[2,376 bytes]
262. (hist) ‎Design of a Fused Multiply Add Floating Point Unit ‎[2,379 bytes]
263. (hist) ‎RedCap-5G for IOT application on prototype taped-out silicon ‎[2,384 bytes]
264. (hist) ‎EEG artifact detection for epilepsy monitoring ‎[2,399 bytes]
265. (hist) ‎High-Throughput Hardware Implementations of Authenticated Encryption Algorithms ‎[2,403 bytes]
266. (hist) ‎Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) ‎[2,404 bytes]
267. (hist) ‎High-Resolution, Calibrated Folding ADCs ‎[2,409 bytes]
268. (hist) ‎Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure ‎[2,411 bytes]
269. (hist) ‎Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration ‎[2,413 bytes]
270. (hist) ‎Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) ‎[2,414 bytes]
271. (hist) ‎Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich) ‎[2,418 bytes]
272. (hist) ‎Watchdog Timer for PULP ‎[2,421 bytes]
273. (hist) ‎LightProbe - 200G Remote DMA for GPU FPGA Data Transfers ‎[2,437 bytes]
274. (hist) ‎DMA Streaming Co-processor ‎[2,439 bytes]
275. (hist) ‎Image and Video Processing ‎[2,447 bytes]
276. (hist) ‎FPGA-Based Digital Frontend for 3G Receivers ‎[2,452 bytes]
277. (hist) ‎Ultra-low power sampling front-end for acquisition of physiological signals ‎[2,460 bytes]
278. (hist) ‎Analog Layout Engine ‎[2,468 bytes]
279. (hist) ‎Active-Set QP Solver on FPGA ‎[2,468 bytes]
280. (hist) ‎Brunn test ‎[2,468 bytes]
281. (hist) ‎Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator ‎[2,469 bytes]
282. (hist) ‎Extending our FPU with Internal High-Precision Accumulation (M) ‎[2,475 bytes]
283. (hist) ‎SystemVerilog formatter for our LowRISC-based guidelines (2-3G) ‎[2,479 bytes]
284. (hist) ‎Eye movements ‎[2,489 bytes]
285. (hist) ‎Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) ‎[2,493 bytes]
286. (hist) ‎Development of a Rockfall Sensor Node ‎[2,498 bytes]
287. (hist) ‎Build the Fastest 2G Modem Ever ‎[2,499 bytes]
288. (hist) ‎Sensor Fusion for Rockfall Sensor Node ‎[2,502 bytes]
289. (hist) ‎Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision ‎[2,509 bytes]
290. (hist) ‎Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces ‎[2,512 bytes]
291. (hist) ‎Compressed Sensing for Wireless Biosignal Monitoring ‎[2,514 bytes]
292. (hist) ‎Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon ‎[2,519 bytes]
293. (hist) ‎Successive Interference Cancellation for 3G Downlink ‎[2,529 bytes]
294. (hist) ‎Implementing A Low-Power Sensor Node Network ‎[2,535 bytes]
295. (hist) ‎Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path ‎[2,537 bytes]
296. (hist) ‎Glitches Reduce Listening Time of Your iPod ‎[2,538 bytes]
297. (hist) ‎A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography ‎[2,538 bytes]
298. (hist) ‎Enhancing our DMA Engine with Fault Tolerance ‎[2,539 bytes]
299. (hist) ‎Influence of the Initial Filament Geometry on the Forming Step in CBRAM ‎[2,542 bytes]
300. (hist) ‎Influence of the Initial Filament Geometry on the Forming Step in CBRAM. ‎[2,542 bytes]
301. (hist) ‎Noise Figure Measurement for Cryogenic System ‎[2,544 bytes]
302. (hist) ‎Ultra Low-Power Oscillator ‎[2,548 bytes]
303. (hist) ‎Sandro Belfanti ‎[2,554 bytes]
304. (hist) ‎Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs ‎[2,554 bytes]
305. (hist) ‎4th Generation Synchronization ‎[2,556 bytes]
306. (hist) ‎Stand-Alone Edge Computing with GAP8 ‎[2,563 bytes]
307. (hist) ‎Neural Networks Framwork for Embedded Plattforms ‎[2,569 bytes]
308. (hist) ‎High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS ‎[2,570 bytes]
309. (hist) ‎Design of Time-Encoded Spiking Neural Networks (IBM-Zurich) ‎[2,589 bytes]
310. (hist) ‎Digital Transmitter for Cellular IoT ‎[2,591 bytes]
311. (hist) ‎Ambient RF Energy harvesting for Wireless Sensor Network ‎[2,592 bytes]
312. (hist) ‎LightProbe - Thermal-Power aware on-head Beamforming ‎[2,593 bytes]
313. (hist) ‎Design of low-offset dynamic comparators ‎[2,598 bytes]
314. (hist) ‎Data Mapping for Unreliable Memories ‎[2,599 bytes]
315. (hist) ‎Battery indifferent wearable Ultrasound ‎[2,602 bytes]
316. (hist) ‎Design of a VLIW processor architecture based on RISC-V ‎[2,607 bytes]
317. (hist) ‎Minimal Cost RISC-V core ‎[2,607 bytes]
318. (hist) ‎A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) ‎[2,607 bytes]
319. (hist) ‎Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich) ‎[2,609 bytes]
320. (hist) ‎Assessment of novel photovoltaic architectures by circuit simulation ‎[2,613 bytes]
321. (hist) ‎DigitalUltrasoundHead ‎[2,613 bytes]
322. (hist) ‎Network-on-Chip for coherent and non-coherent traffic (M) ‎[2,613 bytes]
323. (hist) ‎High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging ‎[2,617 bytes]
324. (hist) ‎Investigation of the source starvation effect in III-V MOSFET ‎[2,619 bytes]
325. (hist) ‎On-Board Software for PULP on a Satellite ‎[2,619 bytes]
326. (hist) ‎Inductive Charging Circuit for Implantable Devices ‎[2,622 bytes]
327. (hist) ‎Ultrasound based hand gesture recognition ‎[2,626 bytes]
328. (hist) ‎A Wearable System for long term monitoring of human physiological parameters with E skin sensors ‎[2,634 bytes]
329. (hist) ‎Charging System for Implantable Electronics ‎[2,642 bytes]
330. (hist) ‎Energy Efficient SoCs ‎[2,643 bytes]
331. (hist) ‎PVT Dynamic Adaptation in PULPv3 ‎[2,644 bytes]
332. (hist) ‎CPS Software-Configurable State-Machine ‎[2,649 bytes]
333. (hist) ‎Design of combined Ultrasound and PPG systems ‎[2,650 bytes]
334. (hist) ‎Resource Partitioning of Caches ‎[2,652 bytes]
335. (hist) ‎Pulse Oximetry Fachpraktikum ‎[2,655 bytes]
336. (hist) ‎MatPHY: An Open-Source Physical Layer Development Framework ‎[2,656 bytes]
337. (hist) ‎Design and Implementation of an Approximate Floating Point Unit ‎[2,661 bytes]
338. (hist) ‎Application Specific Frequency Synthesizers (Analog/Digital PLLs) ‎[2,667 bytes]
339. (hist) ‎An Efficient Compiler Backend for Snitch (1S/B) ‎[2,667 bytes]
340. (hist) ‎Evaluating the RiscV Architecture ‎[2,671 bytes]
341. (hist) ‎Gomeza old project5 ‎[2,671 bytes]
342. (hist) ‎Learning Image Compression with Convolutional Networks ‎[2,674 bytes]
343. (hist) ‎Digital Transmitter for Mobile Communications ‎[2,679 bytes]
344. (hist) ‎Electrothermal characterization of van der Waals Heterostructures with a partial overlap ‎[2,686 bytes]
345. (hist) ‎Design of an LTE Module for the Internet of Things ‎[2,688 bytes]
346. (hist) ‎Image Sensor Interface and Pre-processing ‎[2,695 bytes]
347. (hist) ‎Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces ‎[2,702 bytes]
348. (hist) ‎On-chip clock synthesizer design and porting ‎[2,703 bytes]
349. (hist) ‎Simulation of Li-ion batteries and comparison with experimental data ‎[2,705 bytes]
350. (hist) ‎Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) ‎[2,710 bytes]
351. (hist) ‎Improving datarate and efficiency of ultra low power wearable ultrasound ‎[2,711 bytes]
352. (hist) ‎Analog Compute-in-Memory Accelerator Interface and Integration ‎[2,712 bytes]
353. (hist) ‎Quantum transport in 2D heterostructures ‎[2,725 bytes]
354. (hist) ‎High performance continous-time Delta-Sigma ADC for biomedical applications ‎[2,725 bytes]
355. (hist) ‎Advanced 5G Repetition Combining ‎[2,727 bytes]
356. (hist) ‎Improved Reacquisition for the 5G Cellular IoT ‎[2,733 bytes]
357. (hist) ‎Quantum Transport Modeling of Interband Cascade Lasers (ICL) ‎[2,742 bytes]
358. (hist) ‎Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools ‎[2,743 bytes]
359. (hist) ‎Accelerator for Boosted Binary Features ‎[2,755 bytes]
360. (hist) ‎Channel Estimation and Equalization for LTE Advanced ‎[2,762 bytes]
361. (hist) ‎LightProbe - Design of a High-Speed Optical Link ‎[2,767 bytes]
362. (hist) ‎Wireless EEG Acquisition and Processing ‎[2,769 bytes]
363. (hist) ‎Design of MEMs Sensor Interface ‎[2,771 bytes]
364. (hist) ‎Spatio-Temporal Video Filtering ‎[2,778 bytes]
365. (hist) ‎CMOS power amplifier for field measurements in MRI systems ‎[2,781 bytes]
366. (hist) ‎Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE ‎[2,783 bytes]
367. (hist) ‎Smart Meters ‎[2,783 bytes]
368. (hist) ‎Power Optimization in Multipliers ‎[2,785 bytes]
369. (hist) ‎Design study of tunneling transistors based on a core/shell nanowire structures ‎[2,789 bytes]
370. (hist) ‎Wireless Communication Systems for the IoT ‎[2,790 bytes]
371. (hist) ‎Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) ‎[2,793 bytes]
372. (hist) ‎Resource Partitioning of RPC DRAM ‎[2,796 bytes]
373. (hist) ‎Automatic unplugging detection for Ultrasound probes ‎[2,797 bytes]
374. (hist) ‎Jammer Mitigation Meets Machine Learning ‎[2,797 bytes]
375. (hist) ‎Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication ‎[2,801 bytes]
376. (hist) ‎Design of Streaming Data Platform for High-Speed ADC Data ‎[2,801 bytes]
377. (hist) ‎Gomeza old project3 ‎[2,806 bytes]
378. (hist) ‎Design of a 25 Gbps SerDes for optical chip-to-chip communication ‎[2,809 bytes]
379. (hist) ‎3D Turbo Decoder ASIC Realization ‎[2,810 bytes]
380. (hist) ‎Ultrasound Doppler system development ‎[2,817 bytes]
381. (hist) ‎Analog ‎[2,818 bytes]
382. (hist) ‎Coherence-Capable Write-Back L1 Data Cache for Ariane (M) ‎[2,818 bytes]
383. (hist) ‎Accelerator for Spatio-Temporal Video Filtering ‎[2,819 bytes]
384. (hist) ‎Gomeza old project2 ‎[2,821 bytes]
385. (hist) ‎Ultra low power wearable ultrasound probe ‎[2,821 bytes]
386. (hist) ‎Next Generation Synchronization Signals ‎[2,827 bytes]
387. (hist) ‎Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) ‎[2,829 bytes]
388. (hist) ‎An Energy Efficient Brain-Computer Interface using Mr.Wolf ‎[2,830 bytes]
389. (hist) ‎Implementing Hibernation on the ARM Cortex M0 ‎[2,831 bytes]
390. (hist) ‎Ternary Neural Networks for Face Recognition ‎[2,831 bytes]
391. (hist) ‎Computation of Phonon Bandstructure in III-V Nanostructures ‎[2,836 bytes]
392. (hist) ‎Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) ‎[2,846 bytes]
393. (hist) ‎Evolved EDGE Physical Layer Incremental Redundancy Architecture ‎[2,848 bytes]
394. (hist) ‎Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device ‎[2,851 bytes]
395. (hist) ‎Minimum Variance Beamforming for Wearable Ultrasound Probes ‎[2,858 bytes]
396. (hist) ‎Ultrasound High Speed Microbubble Tracking ‎[2,861 bytes]
397. (hist) ‎Testbed Design for Self-sustainable IoT Sensors ‎[2,870 bytes]
398. (hist) ‎Developing High Efficiency Batteries for Electric Cars ‎[2,871 bytes]
399. (hist) ‎StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC ‎[2,873 bytes]
400. (hist) ‎High-Speed SAR ADC for next generation wireless communication in 12nm FinFET ‎[2,874 bytes]
401. (hist) ‎Time Synchronization for 3G Mobile Communications ‎[2,876 bytes]
402. (hist) ‎Wearable Ultrasound for Artery monitoring ‎[2,884 bytes]
403. (hist) ‎Kinetic Energy Harvesting For Autonomous Smart Watches ‎[2,893 bytes]
404. (hist) ‎Hypervisor Extension for Ariane (M) ‎[2,896 bytes]
405. (hist) ‎Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) ‎[2,899 bytes]
406. (hist) ‎Compressed Sensing Reconstruction on FPGA ‎[2,916 bytes]
407. (hist) ‎Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs) ‎[2,916 bytes]
408. (hist) ‎An FPGA-Based Evaluation Platform for Mobile Communications ‎[2,920 bytes]
409. (hist) ‎Optimizing the Pipeline in our Floating Point Architectures (1S) ‎[2,922 bytes]
410. (hist) ‎FPGA acceleration of ultrasound computed tomography for in vivo tumor screening ‎[2,923 bytes]
411. (hist) ‎Circuits and Systems for Nanoelectrode Array Biosensors ‎[2,937 bytes]
412. (hist) ‎Accelerators for object detection and tracking ‎[2,947 bytes]
413. (hist) ‎Radiation Testing of a PULP ASIC ‎[2,955 bytes]
414. (hist) ‎High-Throughput Authenticated Encryption Architectures based on Block Ciphers ‎[2,957 bytes]
415. (hist) ‎Evaluating An Ultra low Power Vision Node ‎[2,958 bytes]
416. (hist) ‎ASIC Development of 5G-NR LDPC Decoder ‎[2,960 bytes]
417. (hist) ‎Designing a Power Management Unit for PULP SoCs ‎[2,969 bytes]
418. (hist) ‎Towards Self Sustainable UAVs ‎[2,970 bytes]
419. (hist) ‎Advanced Data Movers for Modern Neural Networks ‎[2,983 bytes]
420. (hist) ‎EEG-based drowsiness detection ‎[2,995 bytes]
421. (hist) ‎Variability Tolerant Ultra Low Power Cluster ‎[2,997 bytes]
422. (hist) ‎VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE ‎[3,001 bytes]
423. (hist) ‎Andrea Cossettini ‎[3,011 bytes]
424. (hist) ‎Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control ‎[3,027 bytes]
425. (hist) ‎A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) ‎[3,038 bytes]
426. (hist) ‎VLSI Implementation Polar Decoder using High Level Synthesis ‎[3,039 bytes]
427. (hist) ‎Smart e-glasses for concealed recording of EEG signals ‎[3,040 bytes]
428. (hist) ‎Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control ‎[3,058 bytes]
429. (hist) ‎Efficient Search Design for Hyperdimensional Computing ‎[3,062 bytes]
430. (hist) ‎Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications ‎[3,078 bytes]
431. (hist) ‎Investigation of Metal Diffusion in Oxides for CBRAM Applications ‎[3,080 bytes]
432. (hist) ‎Ultrafast Medical Ultrasound imaging on a GPU ‎[3,084 bytes]
433. (hist) ‎Event-Driven Vision on an embedded platform ‎[3,085 bytes]
434. (hist) ‎Integration Of A Smart Vision System ‎[3,086 bytes]
435. (hist) ‎Hardware Accelerated Derivative Pricing ‎[3,088 bytes]
436. (hist) ‎High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT ‎[3,091 bytes]
437. (hist) ‎Development of an implantable Force sensor for orthopedic applications ‎[3,092 bytes]
438. (hist) ‎Vector Processor for In-Memory Computing ‎[3,095 bytes]
439. (hist) ‎Predict eye movement through brain activity ‎[3,095 bytes]
440. (hist) ‎FPGA System Design for Computer Vision with Convolutional Neural Networks ‎[3,100 bytes]
441. (hist) ‎Every individual on the planet should have a real chance to obtain personalized medical therapy ‎[3,103 bytes]
442. (hist) ‎Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device ‎[3,114 bytes]
443. (hist) ‎Real-Time Pedestrian Detection For Privacy Enhancement ‎[3,130 bytes]
444. (hist) ‎Enabling Efficient Systolic Execution on MemPool (M) ‎[3,130 bytes]
445. (hist) ‎Finite Element Simulations of Transistors for Quantum Computing ‎[3,138 bytes]
446. (hist) ‎Autonomous Smart Watches: Hardware and Software Desing ‎[3,139 bytes]
447. (hist) ‎Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings ‎[3,144 bytes]
448. (hist) ‎Putting Together What Fits Together - GrÆStl ‎[3,145 bytes]
449. (hist) ‎Channel Estimation for 5G Cellular IoT and Fast Fading Channels ‎[3,153 bytes]
450. (hist) ‎EEG earbud ‎[3,161 bytes]
451. (hist) ‎Digital Beamforming for Ultrasound Imaging ‎[3,167 bytes]
452. (hist) ‎Shared Correlation Accelerator for an RF SoC ‎[3,167 bytes]
453. (hist) ‎Efficient TNN compression ‎[3,170 bytes]
454. (hist) ‎Implementation of a 2-D model for Li-ion batteries ‎[3,173 bytes]
455. (hist) ‎Satellite Internet of Things ‎[3,173 bytes]
456. (hist) ‎LightProbe - Frontend Firmware and Control Side Channel ‎[3,177 bytes]
457. (hist) ‎Engineering For Kids ‎[3,177 bytes]
458. (hist) ‎Deep Learning for Brain-Computer Interface ‎[3,180 bytes]
459. (hist) ‎Bateryless Heart Rate Monitoring ‎[3,181 bytes]
460. (hist) ‎PULP Freertos with LLVM ‎[3,185 bytes]
461. (hist) ‎Thermal Control of Mobile Devices ‎[3,195 bytes]
462. (hist) ‎NextGenChannelDec ‎[3,196 bytes]
463. (hist) ‎Advanced EEG glasses ‎[3,216 bytes]
464. (hist) ‎FPGA Testbed Implementation for Bluetooth Indoor Positioning ‎[3,221 bytes]
465. (hist) ‎IoT Turbo Decoder ‎[3,235 bytes]
466. (hist) ‎Augmenting Our IPs with AXI Stream Extensions (M/1-2S) ‎[3,235 bytes]
467. (hist) ‎Using Motion Sensors to Support Indoor Localization ‎[3,236 bytes]
468. (hist) ‎NORX - an AEAD algorithm for the CAESAR competition ‎[3,243 bytes]
469. (hist) ‎High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT ‎[3,248 bytes]
470. (hist) ‎Ultrasound-EMG combined hand gesture recognition ‎[3,248 bytes]
471. (hist) ‎Design of combined Ultrasound and Electromyography systems ‎[3,250 bytes]
472. (hist) ‎Gomeza old project1 ‎[3,251 bytes]
473. (hist) ‎FPGA Optimizations of Dense Binary Hyperdimensional Computing ‎[3,251 bytes]
474. (hist) ‎Heterogeneous SoCs ‎[3,257 bytes]
475. (hist) ‎Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) ‎[3,265 bytes]
476. (hist) ‎CLIC for the CVA6 ‎[3,299 bytes]
477. (hist) ‎Neural Recording Interface and Signal Processing ‎[3,302 bytes]
478. (hist) ‎VLSI Implementation of a 5G Ciphering Accelerator ‎[3,312 bytes]
479. (hist) ‎Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip ‎[3,329 bytes]
480. (hist) ‎Simulation of Negative Capacitance Ferroelectric Transistor ‎[3,335 bytes]
481. (hist) ‎Linux Driver for fine-grain and low overhead access to on-chip performance counters ‎[3,337 bytes]
482. (hist) ‎LTE IoT Network Synchronization ‎[3,346 bytes]
483. (hist) ‎Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) ‎[3,351 bytes]
484. (hist) ‎Next Generation Channel Decoder ‎[3,360 bytes]
485. (hist) ‎A Wireless Sensor Network for a Smart LED Lighting control ‎[3,364 bytes]
486. (hist) ‎Multi issue OoO Ariane Backend (M) ‎[3,365 bytes]
487. (hist) ‎Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) ‎[3,370 bytes]
488. (hist) ‎Low-power chip-to-chip communication network ‎[3,375 bytes]
489. (hist) ‎Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) ‎[3,375 bytes]
490. (hist) ‎Ab-initio Simulation of Strained Thermoelectric Materials ‎[3,382 bytes]
491. (hist) ‎Low-power Clock Generation Solutions for 65nm Technology ‎[3,387 bytes]
492. (hist) ‎Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device ‎[3,394 bytes]
493. (hist) ‎FPGA mapping of RPC DRAM ‎[3,396 bytes]
494. (hist) ‎Real-time Linux on RISC-V ‎[3,402 bytes]
495. (hist) ‎Charge and heat transport through graphene nanoribbon based devices ‎[3,419 bytes]
496. (hist) ‎Compiler Profiling and Optimizing ‎[3,423 bytes]
497. (hist) ‎Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment ‎[3,425 bytes]
498. (hist) ‎Hardware Accelerator for Model Predictive Controller ‎[3,433 bytes]
499. (hist) ‎Cell Measurements for the 5G Internet of Things ‎[3,433 bytes]
500. (hist) ‎Hyper Meccano: Acceleration of Hyperdimensional Computing ‎[3,434 bytes]

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