Pages that link to "Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA"
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The following pages link to Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA:
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- First ASIC Realization For A New HSPA/HSPA+ Detector (redirect page) (← links)