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- (M): A Flexible Peripheral System for High-Performance Systems on Chip
- 3D Turbo Decoder ASIC Realization
- 3D Ultrasound Bubble Tracking
- 4th Generation Synchronization
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- AMZ Driverless Competition Embedded Systems Projects
- ASIC
- ASIC Design Projects
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASIC Implementation of Jammer Mitigation
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A Recurrent Neural Network Speech Recognition Chip
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Snitch-based Compute Accelerator for HERO
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Trustworthy Three-Factor Authentication System
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for HPC monitoring
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A computational memory unit using phase-change memory devices
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- Ab-initio Simulation of Strained Thermoelectric Materials
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
- Acceleration and Transprecision
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accelerators for object detection and tracking
- Accurate deep learning inference using computational memory
- Active-Set QP Solver on FPGA
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Aliasing-Free Wavetable Music Synthesizer
- All-Digital In-Memory Processing
- Ambient RF Energy harvesting for Wireless Sensor Network
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Evaluation Platform for Mobile Communications
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An Industrial-grade Bluetooth LE Mesh Network Solution
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- Analog
- AnalogInt
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analog IC Design
- Analog Layout Engine
- Analog building blocks for mmWave manipulation
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Andrea Cossettini
- Andreas Kurth
- Android Software Design
- Android reliability governor
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Assessment of novel photovoltaic architectures by circuit simulation
- Atretter
- Audio
- Audio DAC Conversion Jitter Measurement System
- Audio Signal Processing
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- Automatic unplugging detection for Ultrasound probes
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Autonomous Sensing For Trains In The IoT Era
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Watches: Hardware and Software Desing
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- BCI-controlled Drone
- BLISS - Battery-Less Identification System for Security
- Bandgap voltage reference in 65nm CMOS
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
- Baseband Meets CPU
- Baseband Processor Development for 4G IoT
- Bateryless Heart Rate Monitoring
- Battery Tester
- Battery indifferent wearable Ultrasound
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Beat Cadence
- Beat DigRF
- Benjamin Sporrer
- Benjamin Weber
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions