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- (M): A Flexible Peripheral System for High-Performance Systems on Chip
- 3D Matrix Multiplication Unit for ITA (1S)
- 3D Turbo Decoder ASIC Realization
- 3D Ultrasound Bubble Tracking
- 4th Generation Synchronization
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- AMZ Driverless Competition Embedded Systems Projects
- ASIC
- ASIC Design Projects
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASIC Implementation of Jammer Mitigation
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
- ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
- ASIC implementation of an interpolation-based wideband massive MIMO detector
- ASR-Waveformer
- AXI-based Network on Chip (NoC) system
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks