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- (M): A Flexible Peripheral System for High-Performance Systems on Chip
- 3D Turbo Decoder ASIC Realization
- 3D Ultrasound Bubble Tracking
- 4th Generation Synchronization
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- AMZ Driverless Competition Embedded Systems Projects
- ASIC
- ASIC Design Projects
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASIC Implementation of Jammer Mitigation
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A Recurrent Neural Network Speech Recognition Chip
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Snitch-based Compute Accelerator for HERO
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Trustworthy Three-Factor Authentication System
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for HPC monitoring
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A computational memory unit using phase-change memory devices
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- Ab-initio Simulation of Strained Thermoelectric Materials
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
- Acceleration and Transprecision
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accelerators for object detection and tracking
- Accurate deep learning inference using computational memory
- Active-Set QP Solver on FPGA
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Aliasing-Free Wavetable Music Synthesizer
- All-Digital In-Memory Processing
- Ambient RF Energy harvesting for Wireless Sensor Network
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Evaluation Platform for Mobile Communications
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An Industrial-grade Bluetooth LE Mesh Network Solution
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- Analog
- AnalogInt
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analog IC Design
- Analog Layout Engine
- Analog building blocks for mmWave manipulation
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Andrea Cossettini
- Andreas Kurth
- Android Software Design
- Android reliability governor
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- Assessment of novel photovoltaic architectures by circuit simulation
- Atretter
- Audio
- Audio DAC Conversion Jitter Measurement System
- Audio Signal Processing
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning
- Automatic unplugging detection for Ultrasound probes
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Autonomous Sensing For Trains In The IoT Era
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Autonomous Smart Watches: Hardware and Software Desing
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- BCI-controlled Drone
- BLISS - Battery-Less Identification System for Security
- Bandgap voltage reference in 65nm CMOS
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
- Baseband Meets CPU
- Baseband Processor Development for 4G IoT
- Bateryless Heart Rate Monitoring
- Battery Tester
- Battery indifferent wearable Ultrasound
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Beat Cadence
- Beat DigRF
- Benjamin Sporrer
- Benjamin Weber
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Biomedical Circuits, Systems, and Applications
- Biomedical System on Chips
- Biomedical Systems on Chip
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Bluetooth Low Energy network with optimized data throughput
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringing XNOR-nets (ConvNets) to Silicon
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- Brunn test
- Build the Fastest 2G Modem Ever
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- CPS Software-Configurable State-Machine
- Cell-Free mmWave Massive MIMO Communication
- Cell Measurements for the 5G Internet of Things
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation and Equalization for LTE Advanced
- Channel Estimation for 3GPP TD-SCDMA
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- Channel Estimation for TD-HSPA
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
- Characterization techniques for silicon photonics-Lumiphase
- Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS
- Charging System for Implantable Electronics
- Christoph Keller
- Circuits and Systems for Nanoelectrode Array Biosensors
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
- Coding Guidelines
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
- Compiler Profiling and Optimizing
- Completed
- Compressed Sensing Reconstruction on FPGA
- Compressed Sensing for Wireless Biosignal Monitoring
- Compressed Sensing vs JPEG
- Compression of Ultrasound data on FPGA
- Compression of iEEG Data
- Computation of Phonon Bandstructure in III-V Nanostructures
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Creating a HDMI Video Interface for PULP
- Cryptography
- DC-DC Buck converter in 65nm CMOS
- DMA Streaming Co-processor
- DaCe on Snitch
- Data Augmentation Techniques in Biosignal Classification
- Data Interface: SPI to PC Bridge for ASICs
- Data Mapping for Unreliable Memories
- David J. Mack
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
- Deep Convolutional Autoencoder for iEEG Signals
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Deep Learning Projects
- Deep Learning for Brain-Computer Interface
- Deep Unfolding of Iterative Optimization Algorithms
- Deep neural networks for seizure detection
- Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- Design Review
- Design and Evaluation of a Small Size Avalanche Beacon
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Design and Implementation of an Approximate Floating Point Unit
- Design and Implementation of ultra low power vision system
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design and implementation of the front-end for a portable ionizing radiation detector
- Design of Charge-Pump PLL in 22nm for 5G communication applications
- Design of MEMs Sensor Interface
- Design of Scalable Event-driven Neural-Recording Digital Interface
- Design of State Retentive Flip-Flops
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
- Design of a Fused Multiply Add Floating Point Unit
- Design of a VLIW processor architecture based on RISC-V
- Design of an LTE Module for the Internet of Things
- Design of an Ultra-Reliable Low-Latency Modem
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
- Design of combined Ultrasound and Electromyography systems
- Design of low-offset dynamic comparators
- Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- Design study of tunneling transistors based on a core/shell nanowire structures
- Designing a Power Management Unit for PULP SoCs
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Developing High Efficiency Batteries for Electric Cars
- Developing a small portable neutron detector for detecting smuggled nuclear material
- Development of a Rockfall Sensor Node
- Development of a fingertip blood pressure sensor
- Development of a syringe label reader for the neurocritical care unit
- Development of an efficient algorithm for quantum transport codes
- Development of an implantable Force sensor for orthopedic applications
- Digital
- DigitalUltrasoundHead
- Digital Audio Interface for Smart Intensive Computing Triggering
- Digital Audio Processor for Cellular Applications
- Digital Beamforming for Ultrasound Imaging
- Digital Front End Design & Frequency Offset Estimation for V2X Communications
- Digital Medical Ultrasound Imaging
- Digital Transmitter for Cellular IoT
- Digital Transmitter for Mobile Communications
- Digitally-Controlled Analog Subtractive Sound Synthesis
- EECIS
- EEG artifact detection for epilepsy monitoring
- EEG artifact detection with machine learning
- Edge Computing for Long-Term Wearable Biomedical Systems
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Search Design for Hyperdimensional Computing
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN Inference on PULP Systems
- Efficient TNN compression
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Elliptic Curve Accelerator for zkSNARKs
- Embedded Artificial Intelligence:Systems And Applications
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Embedded Systems and autonomous UAVs
- Enabling Standalone Operation
- Enabling Standalone Operation for a Mobile Health Platform
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Energy Efficient Autonomous UAVs
- Energy Efficient Circuits and IoT Systems Group
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Efficient SoCs
- Energy Neutral Multi Sensors Wearable Device
- Engineering For Kids
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- EvalEDGE: A 2G Cellular Transceiver FMC
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Computing
- Event-Driven Convolutional Neural Network Modular Accelerator
