Personal tools

Pages without language links

From iis-projects

Jump to: navigation, search

The following pages do not link to other language versions.

Showing below up to 250 results in range #1 to #250.

View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)

  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. 3D Turbo Decoder ASIC Realization
  3. 3D Ultrasound Bubble Tracking
  4. 4th Generation Synchronization
  5. 5G Cellular RF Front-end Design in 22nm CMOS Technology
  6. AMZ Driverless Competition Embedded Systems Projects
  7. ASIC
  8. ASIC Design Projects
  9. ASIC Design of a Gaussian Message Passing Processor
  10. ASIC Design of a Sigma Point Processor
  11. ASIC Development of 5G-NR LDPC Decoder
  12. ASIC Implementation of High-Throughput Next Generation Turbo Decoders
  13. ASIC Implementation of Jammer Mitigation
  14. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
  15. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
  16. A Flexible Peripheral System for High-Performance Systems on Chip (M)
  17. A Multiview Synthesis Core in 65 nm CMOS
  18. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
  19. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
  20. A Recurrent Neural Network Speech Recognition Chip
  21. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  22. A Snitch-based Compute Accelerator for HERO
  23. A Snitch-based Compute Accelerator for HERO (M/1-2S)
  24. A Trustworthy Three-Factor Authentication System
  25. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  26. A Unified Compute Kernel Library for Snitch (1-2S)
  27. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  28. A Wearable System To Control Phone And Electronic Device Without Hands
  29. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
  30. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  31. A Wireless Sensor Network for HPC monitoring
  32. A Wireless Sensor Network for a Smart Building Monitor and Control
  33. A Wireless Sensor Network for a Smart LED Lighting control
  34. A computational memory unit using phase-change memory devices
  35. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
  36. Ab-initio Simulation of Strained Thermoelectric Materials
  37. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  38. Acceleration and Transprecision
  39. Accelerator for Boosted Binary Features
  40. Accelerator for Spatio-Temporal Video Filtering
  41. Accelerators for object detection and tracking
  42. Accurate deep learning inference using computational memory
  43. Active-Set QP Solver on FPGA
  44. Adding Linux Support to our DMA Engine (1-2S/B)
  45. Advanced 5G Repetition Combining
  46. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
  47. Aliasing-Free Wavetable Music Synthesizer
  48. All-Digital In-Memory Processing
  49. Ambient RF Energy harvesting for Wireless Sensor Network
  50. An Energy Efficient Brain-Computer Interface using Mr.Wolf
  51. An FPGA-Based Evaluation Platform for Mobile Communications
  52. An FPGA-Based Testbed for 3G Mobile Communications Receivers
  53. An Industrial-grade Bluetooth LE Mesh Network Solution
  54. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  55. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  56. Analog
  57. AnalogInt
  58. Analog Compute-in-Memory Accelerator Interface and Integration
  59. Analog IC Design
  60. Analog Layout Engine
  61. Analog building blocks for mmWave manipulation
  62. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
  63. Andrea Cossettini
  64. Andreas Kurth
  65. Android Software Design
  66. Android reliability governor
  67. Application Specific Frequency Synthesizers (Analog/Digital PLLs)
  68. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
  69. Assessment of novel photovoltaic architectures by circuit simulation
  70. Atretter
  71. Audio
  72. Audio DAC Conversion Jitter Measurement System
  73. Audio Signal Processing
  74. Audio Video Preprocessing In Parallel Ultra Low Power Platform
  75. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  76. Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  77. Automatic unplugging detection for Ultrasound probes
  78. Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
  79. Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
  80. Autonomous Sensing For Trains In The IoT Era
  81. Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
  82. Autonomous Smart Watches: Hardware and Software Desing
  83. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  84. Autonomus Drones With Novel Sensors And Ultra Wide Band
  85. BCI-controlled Drone
  86. BLISS - Battery-Less Identification System for Security
  87. Bandgap voltage reference in 65nm CMOS
  88. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
  89. Baseband Meets CPU
  90. Baseband Processor Development for 4G IoT
  91. Bateryless Heart Rate Monitoring
  92. Battery Tester
  93. Battery indifferent wearable Ultrasound
  94. Beamspace processing for 5G mmWave massive MIMO on GPU
  95. Beat Cadence
  96. Beat DigRF
  97. Benjamin Sporrer
  98. Benjamin Weber
  99. BigPULP: Multicluster Synchronization Extensions
  100. BigPULP: Shared Virtual Memory Multicluster Extensions
  101. Biomedical Circuits, Systems, and Applications
  102. Biomedical System on Chips
  103. Biomedical Systems on Chip
  104. Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  105. Bluetooth Low Energy network with optimized data throughput
  106. Bluetooth Low Energy receiver in 65nm CMOS
  107. Bridging QuantLab with LPDNN
  108. Bringing XNOR-nets (ConvNets) to Silicon
  109. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  110. Brunn test
  111. Build the Fastest 2G Modem Ever
  112. CLIC for the CVA6
  113. CMOS power amplifier for field measurements in MRI systems
  114. CPS Software-Configurable State-Machine
  115. Cell-Free mmWave Massive MIMO Communication
  116. Cell Measurements for the 5G Internet of Things
  117. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  118. Change-based Evaluation of Convolutional Neural Networks
  119. Channel Decoding for TD-HSPA
  120. Channel Estimation and Equalization for LTE Advanced
  121. Channel Estimation for 3GPP TD-SCDMA
  122. Channel Estimation for 5G Cellular IoT and Fast Fading Channels
  123. Channel Estimation for TD-HSPA
  124. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
  125. Characterization techniques for silicon photonics-Lumiphase
  126. Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS
  127. Charging System for Implantable Electronics
  128. Christoph Keller
  129. Circuits and Systems for Nanoelectrode Array Biosensors
  130. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  131. Coding Guidelines
  132. Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
  133. Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  134. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
  135. Compiler Profiling and Optimizing
  136. Completed
  137. Compressed Sensing Reconstruction on FPGA
  138. Compressed Sensing for Wireless Biosignal Monitoring
  139. Compressed Sensing vs JPEG
  140. Compression of Ultrasound data on FPGA
  141. Compression of iEEG Data
  142. Computation of Phonon Bandstructure in III-V Nanostructures
  143. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
  144. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
  145. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  146. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  147. Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  148. Covariant Feature Detector on Parallel Ultra Low Power Architecture
  149. Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
  150. Creating a HDMI Video Interface for PULP
  151. Cryptography
  152. DC-DC Buck converter in 65nm CMOS
  153. DMA Streaming Co-processor
  154. DaCe on Snitch
  155. Data Augmentation Techniques in Biosignal Classification
  156. Data Interface: SPI to PC Bridge for ASICs
  157. Data Mapping for Unreliable Memories
  158. David J. Mack
  159. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  160. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  161. Deep Convolutional Autoencoder for iEEG Signals
  162. Deep Learning-based Global Local Planner for Autonomous Nano-drones
  163. Deep Learning Projects
  164. Deep Learning for Brain-Computer Interface
  165. Deep Unfolding of Iterative Optimization Algorithms
  166. Deep neural networks for seizure detection
  167. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  168. Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
  169. Design Review
  170. Design and Evaluation of a Small Size Avalanche Beacon
  171. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
  172. Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  173. Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  174. Design and Implementation of a multi-mode multi-master I2C peripheral
  175. Design and Implementation of an Approximate Floating Point Unit
  176. Design and Implementation of ultra low power vision system
  177. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
  178. Design and implementation of the front-end for a portable ionizing radiation detector
  179. Design of Charge-Pump PLL in 22nm for 5G communication applications
  180. Design of MEMs Sensor Interface
  181. Design of Scalable Event-driven Neural-Recording Digital Interface
  182. Design of State Retentive Flip-Flops
  183. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  184. Design of a 25 Gbps SerDes for optical chip-to-chip communication
  185. Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
  186. Design of a Fused Multiply Add Floating Point Unit
  187. Design of a VLIW processor architecture based on RISC-V
  188. Design of an LTE Module for the Internet of Things
  189. Design of an Ultra-Reliable Low-Latency Modem
  190. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
  191. Design of combined Ultrasound and Electromyography systems
  192. Design of low-offset dynamic comparators
  193. Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  194. Design study of tunneling transistors based on a core/shell nanowire structures
  195. Designing a Power Management Unit for PULP SoCs
  196. Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  197. Developing High Efficiency Batteries for Electric Cars
  198. Developing a small portable neutron detector for detecting smuggled nuclear material
  199. Development of a Rockfall Sensor Node
  200. Development of a fingertip blood pressure sensor
  201. Development of a syringe label reader for the neurocritical care unit
  202. Development of an efficient algorithm for quantum transport codes
  203. Development of an implantable Force sensor for orthopedic applications
  204. Digital
  205. DigitalUltrasoundHead
  206. Digital Audio Interface for Smart Intensive Computing Triggering
  207. Digital Audio Processor for Cellular Applications
  208. Digital Beamforming for Ultrasound Imaging
  209. Digital Front End Design & Frequency Offset Estimation for V2X Communications
  210. Digital Medical Ultrasound Imaging
  211. Digital Transmitter for Cellular IoT
  212. Digital Transmitter for Mobile Communications
  213. Digitally-Controlled Analog Subtractive Sound Synthesis
  214. EECIS
  215. EEG artifact detection for epilepsy monitoring
  216. EEG artifact detection with machine learning
  217. Edge Computing for Long-Term Wearable Biomedical Systems
  218. Efficient Implementation of an Active-Set QP Solver for FPGAs
  219. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  220. Efficient NB-IoT Uplink Design
  221. Efficient Search Design for Hyperdimensional Computing
  222. Efficient Synchronization of Manycore Systems (M/1S)
  223. Efficient TNN Inference on PULP Systems
  224. Efficient TNN compression
  225. Electrothermal characterization of van der Waals Heterostructures with a partial overlap
  226. Elliptic Curve Accelerator for zkSNARKs
  227. Embedded Artificial Intelligence:Systems And Applications
  228. Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  229. Embedded Gesture Recognition Using Novel Mini Radar Sensors
  230. Embedded Systems and autonomous UAVs
  231. Enabling Standalone Operation
  232. Enabling Standalone Operation for a Mobile Health Platform
  233. Energy-Efficient Brain-Inspired Hyperdimensional Computing
  234. Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
  235. Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
  236. Energy Efficient Autonomous UAVs
  237. Energy Efficient Circuits and IoT Systems Group
  238. Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
  239. Energy Efficient SoCs
  240. Energy Neutral Multi Sensors Wearable Device
  241. Engineering For Kids
  242. Enhancing our DMA Engine with Fault Tolerance
  243. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
  244. EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
  245. EvalEDGE: A 2G Cellular Transceiver FMC
  246. Evaluating An Ultra low Power Vision Node
  247. Evaluating SoA Post-Training Quantization Algorithms
  248. Evaluating memory access pattern specializations in OoO, server-grade cores (M)
  249. Evaluating the RiscV Architecture
  250. Event-Driven Computing

View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)