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Showing below up to 250 results in range #1 to #250.

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1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
2. 3D Matrix Multiplication Unit for ITA (1S)
3. 3D Turbo Decoder ASIC Realization
4. 3D Ultrasound Bubble Tracking
5. 4th Generation Synchronization
6. 5G Cellular RF Front-end Design in 22nm CMOS Technology
7. AMZ Driverless Competition Embedded Systems Projects
8. ASIC
9. ASIC Design Projects
10. ASIC Design of a Gaussian Message Passing Processor
11. ASIC Design of a Sigma Point Processor
12. ASIC Development of 5G-NR LDPC Decoder
13. ASIC Implementation of High-Throughput Next Generation Turbo Decoders
14. ASIC Implementation of Jammer Mitigation
15. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
16. ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
17. ASIC implementation of an interpolation-based wideband massive MIMO detector
18. ASR-Waveformer
19. AXI-based Network on Chip (NoC) system
20. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
21. A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
22. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
23. A Flexible Peripheral System for High-Performance Systems on Chip (M)
24. A Multiview Synthesis Core in 65 nm CMOS
25. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
26. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
27. A Post-Simulation Trace-Based RISC-V GDB Debugging Server
28. A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
29. A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
30. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
31. A Recurrent Neural Network Speech Recognition Chip
32. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
33. A Snitch-based Compute Accelerator for HERO
34. A Snitch-based Compute Accelerator for HERO (M/1-2S)
35. A Trustworthy Three-Factor Authentication System
36. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
37. A Unified Compute Kernel Library for Snitch (1-2S)
38. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
39. A Wearable System To Control Phone And Electronic Device Without Hands
40. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
41. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
42. A Wireless Sensor Network for HPC monitoring
43. A Wireless Sensor Network for a Smart Building Monitor and Control
44. A Wireless Sensor Network for a Smart LED Lighting control
45. A computational memory unit using phase-change memory devices
46. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
47. A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
48. Ab-initio Simulation of Strained Thermoelectric Materials
49. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
50. Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
51. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
52. Acceleration and Transprecision
53. Accelerator for Boosted Binary Features
54. Accelerator for Spatio-Temporal Video Filtering
55. Accelerators for object detection and tracking
56. Accurate deep learning inference using computational memory
57. Active-Set QP Solver on FPGA
58. Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
59. Adding Linux Support to our DMA Engine (1-2S/B)
60. Advanced 5G Repetition Combining
61. Advanced Data Movers for Modern Neural Networks
62. Advanced EEG glasses
63. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
64. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
65. Alias-Free Oscillator Synchronization for Arbitrary Waveforms
66. Aliasing-Free Wavetable Music Synthesizer
67. All-Digital In-Memory Processing
68. All the flavours of FFT on MemPool (1-2S/B)
69. Ambient RF Energy harvesting for Wireless Sensor Network
70. An Efficient Compiler Backend for Snitch (1S/B)
71. An Energy Efficient Brain-Computer Interface using Mr.Wolf
72. An FPGA-Based Evaluation Platform for Mobile Communications
73. An FPGA-Based Testbed for 3G Mobile Communications Receivers
74. An Industrial-grade Bluetooth LE Mesh Network Solution
75. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
76. An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
77. An Ultra-Low-Power Neuromorphic Spiking Neuron Design
78. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
79. Analog
80. AnalogInt
81. Analog Compute-in-Memory Accelerator Interface and Integration
82. Analog IC Design
83. Analog Layout Engine
84. Analog building blocks for mmWave manipulation
85. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
86. Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
87. Andrea Cossettini
88. Andreas Kurth
89. Android Software Design
90. Android reliability governor
91. Application Specific Frequency Synthesizers (Analog/Digital PLLs)
92. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
93. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
94. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
95. Artificial Reverberation for Embedded Systems
96. Assessment of novel photovoltaic architectures by circuit simulation
97. Atretter
98. Audio
99. Audio DAC Conversion Jitter Measurement System
100. Audio Signal Processing
101. Audio Video Preprocessing In Parallel Ultra Low Power Platform
102. Audio Visual Speech Recognition (1S/1M)
103. Audio Visual Speech Separation (1S/1M)
104. Audio Visual Speech Separation and Recognition (1S/1M)
105. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
106. Autoencoder Accelerator for On-Chip Semi-Supervised Learning
107. Automatic unplugging detection for Ultrasound probes
108. Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
109. Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
110. Autonomous Sensing For Trains In The IoT Era
111. Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
112. Autonomous Smart Watches: Hardware and Software Desing
113. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
114. Autonomus Drones With Novel Sensors And Ultra Wide Band
115. BCI-controlled Drone
116. BLISS - Battery-Less Identification System for Security
117. Bandwidth Efficient NEureka
118. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
119. Baseband Meets CPU
120. Baseband Processor Development for 4G IoT
121. Bateryless Heart Rate Monitoring
122. Battery indifferent wearable Ultrasound
123. Beamspace processing for 5G mmWave massive MIMO on GPU
124. Beat Cadence
125. Beat DigRF
126. Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
127. Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
128. Benchmarking a heterogeneous 217-core MPSoC on HPC applications
129. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
130. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
131. Benjamin Sporrer
132. Benjamin Weber
133. BigPULP: Multicluster Synchronization Extensions
134. BigPULP: Shared Virtual Memory Multicluster Extensions
135. Big Data Analytics Benchmarks for Ara
136. Biomedical Circuits, Systems, and Applications
137. Biomedical System on Chips
138. Biomedical Systems on Chip
139. BirdGuard
140. Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
141. Bluetooth Low Energy network with optimized data throughput
142. Bluetooth Low Energy receiver in 65nm CMOS
143. Bridging QuantLab with LPDNN
144. Bringing XNOR-nets (ConvNets) to Silicon
145. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
146. Brunn test
147. Build the Fastest 2G Modem Ever
148. Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
149. CLIC for the CVA6
150. CMOS power amplifier for field measurements in MRI systems
151. CPS Software-Configurable State-Machine
152. Cell-Free mmWave Massive MIMO Communication
153. Cell Measurements for the 5G Internet of Things
154. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
155. Change-based Evaluation of Convolutional Neural Networks
156. Channel Decoding for TD-HSPA
157. Channel Estimation and Equalization for LTE Advanced
158. Channel Estimation for 3GPP TD-SCDMA
159. Channel Estimation for 5G Cellular IoT and Fast Fading Channels
160. Channel Estimation for TD-HSPA
161. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
162. Characterization techniques for silicon photonics-Lumiphase
163. Charge and heat transport through graphene nanoribbon based devices
164. Charging System for Implantable Electronics
165. Christoph Keller
166. Christoph Leitner
167. Circuits and Systems for Nanoelectrode Array Biosensors
168. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
169. Coding Guidelines
170. Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
171. Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
172. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
173. Compiler Profiling and Optimizing
174. Completed
175. Compressed Sensing Reconstruction on FPGA
176. Compressed Sensing for Wireless Biosignal Monitoring
177. Compressed Sensing vs JPEG
178. Compression of Ultrasound data on FPGA
179. Compression of iEEG Data
180. Computation of Phonon Bandstructure in III-V Nanostructures
181. Configurable Ultra Low Power LDO
182. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
183. Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
184. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
185. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
186. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
187. Counter-based Fast Power Estimation using FPGAs (M/1-3S)
188. Covariant Feature Detector on Parallel Ultra Low Power Architecture
189. Creating A Boundry Scan Generator (1-3S/B/2-3G)
190. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
191. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
192. Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
193. Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
194. Creating a HDMI Video Interface for PULP
195. Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
196. Cryptography
197. Cycle-Accurate Event-Based Simulation of Snitch Core
198. DC-DC Buck converter in 65nm CMOS
199. DMA Streaming Co-processor
200. DaCe on Snitch
201. Data Augmentation Techniques in Biosignal Classification
202. Data Mapping for Unreliable Memories
203. David J. Mack
204. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
205. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
206. Deep Convolutional Autoencoder for iEEG Signals
207. Deep Learning-based Global Local Planner for Autonomous Nano-drones
208. Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
209. Deep Learning Projects
210. Deep Learning for Brain-Computer Interface
211. Deep Unfolding of Iterative Optimization Algorithms
212. Deep neural networks for seizure detection
213. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
214. Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
215. Design Review
216. Design and Evaluation of a Small Size Avalanche Beacon
217. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
218. Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
219. Design and Implementation of a Convolutional Neural Network Accelerator ASIC
220. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
221. Design and Implementation of a multi-mode multi-master I2C peripheral
222. Design and Implementation of an Approximate Floating Point Unit
223. Design and Implementation of ultra low power vision system
224. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
225. Design and implementation of the front-end for a portable ionizing radiation detector
226. Design of Charge-Pump PLL in 22nm for 5G communication applications
227. Design of MEMs Sensor Interface
228. Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
229. Design of Scalable Event-driven Neural-Recording Digital Interface
230. Design of State Retentive Flip-Flops
231. Design of Streaming Data Platform for High-Speed ADC Data
232. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
233. Design of a 25 Gbps SerDes for optical chip-to-chip communication
234. Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
235. Design of a D-Band Variable Gain Amplifier for 6G Communication
236. Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
237. Design of a Fused Multiply Add Floating Point Unit
238. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
239. Design of a Low Power Smart Sensing Multi-modal Vision Platform
240. Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
241. Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
242. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
243. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
244. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
245. Design of a VLIW processor architecture based on RISC-V
246. Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
247. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
248. Design of an LTE Module for the Internet of Things
249. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
250. Design of combined Ultrasound and Electromyography systems

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