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Showing below up to 250 results in range #251 to #500.

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  1. Event-Driven Convolutional Neural Network Modular Accelerator
  2. Event-Driven Vision on an embedded platform
  3. Every individual on the planet should have a real chance to obtain personalized medical therapy
  4. Evolved EDGE Physical Layer Incremental Redundancy Architecture
  5. Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
  6. Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  7. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  8. Exploring Algorithms for Early Seizure Detection
  9. Exploring Bio Impedance
  10. Exploring NAS spaces with C-BRED
  11. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
  12. Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
  13. Exploring schedules for incremental and annealing quantization algorithms
  14. Extend the RI5CY core with priviledge extensions
  15. Extending the RISCV backend of LLVM to support PULP Extensions
  16. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
  17. Eye movements
  18. Eye tracking
  19. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  20. FFT-based Convolutional Network Accelerator
  21. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  22. FPGA
  23. FPGA-Based Digital Frontend for 3G Receivers
  24. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
  25. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  26. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  27. FPGA System Design for Computer Vision with Convolutional Neural Networks
  28. FPGA Testbed Implementation for Bluetooth Indoor Positioning
  29. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  30. Fabian Schuiki
  31. Fast Accelerator Context Switch for PULP
  32. Fast Simulation of Manycore Systems (1S)
  33. Fast Wakeup From Deep Sleep State
  34. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  35. Fault Tolerance
  36. Feature Extraction for Speech Recognition (1S)
  37. Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  38. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  39. Final Presentation
  40. Final Report
  41. Finite Element Simulations of Transistors for Quantum Computing
  42. Finite element modeling of electrochemical random access memory
  43. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
  44. Flexfloat DL Training Framework
  45. Flexible Front-End Circuit for Biomedical Data Acquisition
  46. Floating-Point Divide & Square Root Unit for Transprecision
  47. Fluffy bunny project
  48. Forward error-correction ASIC using GRAND
  49. Frank K. Gürkaynak
  50. Freedom from Interference in Heterogeneous COTS SoCs
  51. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  52. GRAND Hardware Implementation
  53. GSM Voice Capacity Evolution - VAMOS
  54. GUI-developement for an action-cam-based eye tracking device
  55. Glitches Reduce Listening Time of Your iPod
  56. Gomeza old project1
  57. Gomeza old project2
  58. Gomeza old project3
  59. Gomeza old project4
  60. Gomeza old project5
  61. Graph neural networks for epileptic seizure detection
  62. Guillaume Mocquard
  63. HERO: TLB Invalidation
  64. HW/SW Safety and Security
  65. Harald Kröll
  66. Hardware/software co-programming on the Parallella platform
  67. Hardware/software codesign neural decoding algorithm for “neural dust”
  68. Hardware Accelerated Derivative Pricing
  69. Hardware Acceleration
  70. Hardware Accelerator Integration into Embedded Linux
  71. Hardware Accelerator for Model Predictive Controller
  72. Hardware Accelerators for Lossless Quantized Deep Neural Networks
  73. Hardware Constrained Neural Architechture Search
  74. Hardware Support for IDE in Multicore Environment
  75. Heart Rate Detection Algorithm
  76. Heroino: Design of the next CORE-V Microcontroller
  77. Herschmi
  78. Heterogeneous SoCs
  79. High-Performance & V2X Cellular Communications
  80. High-Resolution, Calibrated Folding ADCs
  81. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  82. High-Speed Channel Estimation & Tracking for V2X Communications
  83. High-Speed DigRF-v4 Implementation
  84. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  85. High-Throughput Channel Coding & Decoding for V2X Communications
  86. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  87. High-speed Scene Labeling on FPGA
  88. High-throughput Embedded System For Neurotechnology in collaboration with INI
  89. High Performance Cellular Receivers in Very Advanced CMOS
  90. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  91. High Performance SoCs
  92. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  93. High Speed FPGA Trigger Logic for Particle Physics Experiments
  94. High Throughput Turbo Decoder Design
  95. High performance continous-time Delta-Sigma ADC for biomedical applications
  96. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  97. Huawei Research
  98. Human Intranet
  99. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  100. Hyper-Dimensional Computing Based Predictive Maintenance
  101. Hyper Meccano: Acceleration of Hyperdimensional Computing
  102. Hyperdimensional Computing
  103. Hypervisor Extension for Ariane (M)
  104. IBM A2O Core
  105. IBM Research
  106. IBM Research–Zurich
  107. IP-Based SoC Generation and Configuration (1-3S)
  108. IP-Based SoC Generation and Configuration (1-3S/B)
  109. ISA extensions in the Snitch Processor for Signal Processing (1M)
  110. ISA extensions in the Snitch Processor for Signal Processing (M)
  111. Ibex: Bit-Manipulation Extension
  112. Ibex: FPGA Optimizations
  113. Ibex: Tightly-Coupled Accelerators and ISA Extensions
  114. IcySoC
  115. Image Sensor Interface and Pre-processing
  116. Image and Video Processing
  117. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  118. Implementation of a 2-D model for Li-ion batteries
  119. Implementation of a Heterogeneous System for Image Processing on an FPGA
  120. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  121. Implementation of a NB-IoT Positioning System
  122. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  123. Implementation of an AES Hardware Processing Engine (B/S)
  124. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
  125. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  126. Implementing A Low-Power Sensor Node Network
  127. Implementing DSP Instructions in Banshee (1S)
  128. Implementing Hibernation on the ARM Cortex M0
  129. Improved Collision Avoidance for Nano-drones
  130. Improved Reacquisition for the 5G Cellular IoT
  131. Improved State Estimation on PULP-based Nano-UAVs
  132. Improving Cold-Start in Batteryless And Energy Harvesting Systems
  133. Improving Resiliency of Hyperdimensional Computing
  134. Improving Scene Labeling with Hyperspectral Data
  135. Improving datarate and efficiency of ultra low power wearable ultrasound
  136. Improving our Smart Camera System
  137. Indoor Positioning with Bluetooth
  138. Indoor Smart Tracking of Hospital instrumentation
  139. Inductive Charging Circuit for Implantable Devices
  140. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
  141. Influence of the Initial Filament Geometry on the Forming Step in CBRAM
  142. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
  143. Infrared Wake Up Radio
  144. Integrated Information Processing
  145. Integrated silicon photonic structures
  146. Integrated silicon photonic structures-Lumiphase
  147. Integrating Hardware Accelerators into Snitch
  148. Integrating Hardware Accelerators into Snitch (1S)
  149. Intelligent Power Management Unit (iPMU)
  150. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  151. Interference Cancellation for EC-GSM-IoT
  152. Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
  153. Interference Cancellation for the cellular Internet of Things
  154. Internet of Things Network Synchronizer
  155. Internet of Things SoC Characterization
  156. Investigation of Metal Diffusion in Oxides for CBRAM Applications
  157. Investigation of Redox Processes in CBRAM
  158. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
  159. Investigation of the source starvation effect in III-V MOSFET
  160. IoT Turbo Decoder
  161. Karim Badawi
  162. Kinetic Energy Harvesting For Autonomous Smart Watches
  163. Knowledge Distillation for Embedded Machine Learning
  165. LLVM and DaCe for Snitch (1-2S)
  166. LTE-Advanced RF Front-end Design in 28nm CMOS Technology
  167. LTE IoT Network Synchronization
  168. Learning Image Compression with Convolutional Networks
  169. Learning Image Decompression with Convolutional Networks
  170. Level Crossing ADC For a Many Channels Neural Recording Interface
  171. Libria
  172. LightProbe
  173. LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
  174. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
  175. LightProbe - CNN-Based-Image-Reconstruction
  176. LightProbe - Design of a High-Speed Optical Link
  177. LightProbe - Frontend Firmware and Control Side Channel
  178. LightProbe - Implementation of compressed-sensing algorithms
  179. LightProbe - Thermal-Power aware on-head Beamforming
  180. LightProbe - Ultracompact Power Supply PCB
  181. LightProbe - WIFI extension (PCB)
  182. Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  183. Linux Driver for fine-grain and low overhead access to on-chip performance counters
  184. Livestream GUI via USB
  185. Low-Complexity MIMO Detection
  186. Low-Dropout Regulators for Magnetic Resonance Imaging
  187. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  188. Low-Power Time Synchronization for IoT Applications
  189. Low-Resolution 5G Beamforming Codebook Design
  190. Low-power Clock Generation Solutions for 65nm Technology
  191. Low-power Temperature-insensitive Timer
  192. Low-power chip-to-chip communication network
  193. Low-power time synchronization for IoT applications
  194. Low Latency Brain-Machine Interfaces
  195. Low Power Embedded Systems
  196. Low Power Embedded Systems and Wireless Sensors Networks
  197. Low Power Geolocalization And Indoor Localization
  198. Low Power Neural Network For Multi Sensors Wearable Devices
  199. Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
  200. Low Resolution Neural Networks
  201. Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
  202. Machine Learning for extracting Muscle features from Ultrasound raw data
  203. Machine Learning for extracting Muscle features using Ultrasound
  204. Machine Learning for extracting Muscle features using Ultrasound 2
  205. Machine Learning on Ultrasound Images
  206. Main Page
  207. Make Cellular Internet of Things Receivers Smart
  208. Manycore System on FPGA (M/S/G)
  209. Mapping Networks on Reconfigurable Binary Engine Accelerator
  210. MatPHY: An Open-Source Physical Layer Development Framework
  211. Matheus Cavalcante
  212. Matteo Perotti
  213. Matthias Korb
  214. Mattia
  215. Mauro Salomon
  216. MemPool on HERO
  217. MemPool on HERO (1S)
  218. Memory Augmented Neural Networks in Brain-Computer Interfaces
  219. Michael Muehlberghuber
  220. Michael Rogenmoser
  221. Minimal Cost RISC-V core
  222. Minimum Variance Beamforming for Wearable Ultrasound Probes
  223. Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  224. Monocular Vision-based Object Following on Nano-size Robotic Blimp
  225. Moritz Schneider
  226. Multi-Band Receiver Design for LTE Mobile Communication
  227. Multi issue OoO Ariane Backend (M)
  228. Multiuser Equalization and Detection for 3GPP TD-SCDMA
  229. NAND Flash Open Research Platform
  230. NORX - an AEAD algorithm for the CAESAR competition
  231. NVDLA meets PULP
  232. Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
  233. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
  234. Near-Memory Training of Neural Networks
  235. Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
  236. Neural Architecture Search using Reinforcement Learning and Search Space Reduction
  237. Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
  238. Neural Networks Framwork for Embedded Plattforms
  239. Neural Processing
  240. Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  241. New RVV 1.0 Vector Instructions for Ara
  242. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
  243. NextGenChannelDec
  244. Next Generation Channel Decoder
  245. Next Generation Synchronization Signals
  246. Nils Wistoff
  247. Non-binary LDPC Decoder for Deep-Space Optical Communications
  248. Non-blocking Algorithms in Real-Time Operating Systems
  249. Norbert Felber
  250. Novel Metastability Mitigation Technique

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