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Showing below up to 50 results in range #51 to #100.

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51. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
52. Acceleration and Transprecision
53. Accelerator for Boosted Binary Features
54. Accelerator for Spatio-Temporal Video Filtering
55. Accelerators for object detection and tracking
56. Accurate deep learning inference using computational memory
57. Active-Set QP Solver on FPGA
58. Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
59. Adding Linux Support to our DMA Engine (1-2S/B)
60. Advanced 5G Repetition Combining
61. Advanced Data Movers for Modern Neural Networks
62. Advanced EEG glasses
63. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
64. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
65. Alias-Free Oscillator Synchronization for Arbitrary Waveforms
66. Aliasing-Free Wavetable Music Synthesizer
67. All-Digital In-Memory Processing
68. All the flavours of FFT on MemPool (1-2S/B)
69. Ambient RF Energy harvesting for Wireless Sensor Network
70. An Efficient Compiler Backend for Snitch (1S/B)
71. An Energy Efficient Brain-Computer Interface using Mr.Wolf
72. An FPGA-Based Evaluation Platform for Mobile Communications
73. An FPGA-Based Testbed for 3G Mobile Communications Receivers
74. An Industrial-grade Bluetooth LE Mesh Network Solution
75. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
76. An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
77. An Ultra-Low-Power Neuromorphic Spiking Neuron Design
78. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
79. Analog
80. AnalogInt
81. Analog Compute-in-Memory Accelerator Interface and Integration
82. Analog IC Design
83. Analog Layout Engine
84. Analog building blocks for mmWave manipulation
85. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
86. Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
87. Andrea Cossettini
88. Andreas Kurth
89. Android Software Design
90. Android reliability governor
91. Application Specific Frequency Synthesizers (Analog/Digital PLLs)
92. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
93. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
94. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
95. Artificial Reverberation for Embedded Systems
96. Assessment of novel photovoltaic architectures by circuit simulation
97. Atretter
98. Audio
99. Audio DAC Conversion Jitter Measurement System
100. Audio Signal Processing

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