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Showing below up to 500 results in range #1 to #500.

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  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. 3D Turbo Decoder ASIC Realization
  3. 3D Ultrasound Bubble Tracking
  4. 4th Generation Synchronization
  5. 5G Cellular RF Front-end Design in 22nm CMOS Technology
  6. AMZ Driverless Competition Embedded Systems Projects
  7. ASIC
  8. ASIC Design Projects
  9. ASIC Design of a Gaussian Message Passing Processor
  10. ASIC Design of a Sigma Point Processor
  11. ASIC Development of 5G-NR LDPC Decoder
  12. ASIC Implementation of High-Throughput Next Generation Turbo Decoders
  13. ASIC Implementation of Jammer Mitigation
  14. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
  15. ASIC implementation of an interpolation-based wideband massive MIMO detector
  16. AXI-based Network on Chip (NoC) system
  17. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
  18. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
  19. A Flexible Peripheral System for High-Performance Systems on Chip (M)
  20. A Multiview Synthesis Core in 65 nm CMOS
  21. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
  22. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
  23. A Post-Simulation Trace-Based RISC-V GDB Debugging Server
  24. A Recurrent Neural Network Speech Recognition Chip
  25. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  26. A Snitch-based Compute Accelerator for HERO
  27. A Snitch-based Compute Accelerator for HERO (M/1-2S)
  28. A Trustworthy Three-Factor Authentication System
  29. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  30. A Unified Compute Kernel Library for Snitch (1-2S)
  31. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  32. A Wearable System To Control Phone And Electronic Device Without Hands
  33. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
  34. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  35. A Wireless Sensor Network for HPC monitoring
  36. A Wireless Sensor Network for a Smart Building Monitor and Control
  37. A Wireless Sensor Network for a Smart LED Lighting control
  38. A computational memory unit using phase-change memory devices
  39. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
  40. A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  41. Ab-initio Simulation of Strained Thermoelectric Materials
  42. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  43. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
  44. Acceleration and Transprecision
  45. Accelerator for Boosted Binary Features
  46. Accelerator for Spatio-Temporal Video Filtering
  47. Accelerators for object detection and tracking
  48. Accurate deep learning inference using computational memory
  49. Active-Set QP Solver on FPGA
  50. Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  51. Adding Linux Support to our DMA Engine (1-2S/B)
  52. Advanced 5G Repetition Combining
  53. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
  54. Alias-Free Oscillator Synchronization for Arbitrary Waveforms
  55. Aliasing-Free Wavetable Music Synthesizer
  56. All-Digital In-Memory Processing
  57. All the flavours of FFT on MemPool (1-2S/B)
  58. Ambient RF Energy harvesting for Wireless Sensor Network
  59. An Efficient Compiler Backend for Snitch (1S/B)
  60. An Energy Efficient Brain-Computer Interface using Mr.Wolf
  61. An FPGA-Based Evaluation Platform for Mobile Communications
  62. An FPGA-Based Testbed for 3G Mobile Communications Receivers
  63. An Industrial-grade Bluetooth LE Mesh Network Solution
  64. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  65. An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
  66. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  67. Analog
  68. AnalogInt
  69. Analog Compute-in-Memory Accelerator Interface and Integration
  70. Analog IC Design
  71. Analog Layout Engine
  72. Analog building blocks for mmWave manipulation
  73. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
  74. Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
  75. Andrea Cossettini
  76. Andreas Kurth
  77. Android Software Design
  78. Android reliability governor
  79. Application Specific Frequency Synthesizers (Analog/Digital PLLs)
  80. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
  81. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
  82. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
  83. Assessment of novel photovoltaic architectures by circuit simulation
  84. Atretter
  85. Audio
  86. Audio DAC Conversion Jitter Measurement System
  87. Audio Signal Processing
  88. Audio Video Preprocessing In Parallel Ultra Low Power Platform
  89. Audio Visual Speech Separation and Recognition (1S/1M)
  90. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  91. Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  92. Automatic unplugging detection for Ultrasound probes
  93. Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
  94. Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
  95. Autonomous Sensing For Trains In The IoT Era
  96. Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
  97. Autonomous Smart Watches: Hardware and Software Desing
  98. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  99. Autonomus Drones With Novel Sensors And Ultra Wide Band
  100. BCI-controlled Drone
  101. BLISS - Battery-Less Identification System for Security
  102. Bandwidth Efficient NEureka
  103. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
  104. Baseband Meets CPU
  105. Baseband Processor Development for 4G IoT
  106. Bateryless Heart Rate Monitoring
  107. Battery indifferent wearable Ultrasound
  108. Beamspace processing for 5G mmWave massive MIMO on GPU
  109. Beat Cadence
  110. Beat DigRF
  111. Benchmarking a heterogeneous 217-core MPSoC on HPC applications
  112. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  113. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
  114. Benjamin Sporrer
  115. Benjamin Weber
  116. BigPULP: Multicluster Synchronization Extensions
  117. BigPULP: Shared Virtual Memory Multicluster Extensions
  118. Big Data Analytics Benchmarks for Ara
  119. Biomedical Circuits, Systems, and Applications
  120. Biomedical System on Chips
  121. Biomedical Systems on Chip
  122. BirdGuard
  123. Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  124. Bluetooth Low Energy network with optimized data throughput
  125. Bluetooth Low Energy receiver in 65nm CMOS
  126. Bridging QuantLab with LPDNN
  127. Bringing XNOR-nets (ConvNets) to Silicon
  128. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  129. Brunn test
  130. Build the Fastest 2G Modem Ever
  131. CLIC for the CVA6
  132. CMOS power amplifier for field measurements in MRI systems
  133. CPS Software-Configurable State-Machine
  134. Cell-Free mmWave Massive MIMO Communication
  135. Cell Measurements for the 5G Internet of Things
  136. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  137. Change-based Evaluation of Convolutional Neural Networks
  138. Channel Decoding for TD-HSPA
  139. Channel Estimation and Equalization for LTE Advanced
  140. Channel Estimation for 3GPP TD-SCDMA
  141. Channel Estimation for 5G Cellular IoT and Fast Fading Channels
  142. Channel Estimation for TD-HSPA
  143. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
  144. Characterization techniques for silicon photonics-Lumiphase
  145. Charge and heat transport through graphene nanoribbon based devices
  146. Charging System for Implantable Electronics
  147. Christoph Keller
  148. Christoph Leitner
  149. Circuits and Systems for Nanoelectrode Array Biosensors
  150. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  151. Coding Guidelines
  152. Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
  153. Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  154. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
  155. Compiler Profiling and Optimizing
  156. Completed
  157. Compressed Sensing Reconstruction on FPGA
  158. Compressed Sensing for Wireless Biosignal Monitoring
  159. Compressed Sensing vs JPEG
  160. Compression of Ultrasound data on FPGA
  161. Compression of iEEG Data
  162. Computation of Phonon Bandstructure in III-V Nanostructures
  163. Configurable Ultra Low Power LDO
  164. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
  165. Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
  166. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
  167. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  168. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  169. Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  170. Covariant Feature Detector on Parallel Ultra Low Power Architecture
  171. Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
  172. Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
  173. Creating a HDMI Video Interface for PULP
  174. Cryptography
  175. DC-DC Buck converter in 65nm CMOS
  176. DMA Streaming Co-processor
  177. DaCe on Snitch
  178. Data Augmentation Techniques in Biosignal Classification
  179. Data Mapping for Unreliable Memories
  180. David J. Mack
  181. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  182. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  183. Deep Convolutional Autoencoder for iEEG Signals
  184. Deep Learning-based Global Local Planner for Autonomous Nano-drones
  185. Deep Learning Projects
  186. Deep Learning for Brain-Computer Interface
  187. Deep Unfolding of Iterative Optimization Algorithms
  188. Deep neural networks for seizure detection
  189. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  190. Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
  191. Design Review
  192. Design and Evaluation of a Small Size Avalanche Beacon
  193. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
  194. Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  195. Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  196. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
  197. Design and Implementation of a multi-mode multi-master I2C peripheral
  198. Design and Implementation of an Approximate Floating Point Unit
  199. Design and Implementation of ultra low power vision system
  200. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
  201. Design and implementation of the front-end for a portable ionizing radiation detector
  202. Design of Charge-Pump PLL in 22nm for 5G communication applications
  203. Design of MEMs Sensor Interface
  204. Design of Scalable Event-driven Neural-Recording Digital Interface
  205. Design of State Retentive Flip-Flops
  206. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  207. Design of a 25 Gbps SerDes for optical chip-to-chip communication
  208. Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
  209. Design of a D-Band Variable Gain Amplifier for 6G Communication
  210. Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
  211. Design of a Fused Multiply Add Floating Point Unit
  212. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
  213. Design of a Low Power Smart Sensing Multi-modal Vision Platform
  214. Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
  215. Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
  216. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
  217. Design of a VLIW processor architecture based on RISC-V
  218. Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
  219. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
  220. Design of an LTE Module for the Internet of Things
  221. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
  222. Design of combined Ultrasound and Electromyography systems
  223. Design of combined Ultrasound and PPG systems
  224. Design of low-offset dynamic comparators
  225. Design of low mismatch DAC used for VAD
  226. Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  227. Design study of tunneling transistors based on a core/shell nanowire structures
  228. Designing a Power Management Unit for PULP SoCs
  229. Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  230. Developing High Efficiency Batteries for Electric Cars
  231. Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
  232. Developing a small portable neutron detector for detecting smuggled nuclear material
  233. Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  234. Development of a Rockfall Sensor Node
  235. Development of a fingertip blood pressure sensor
  236. Development of a syringe label reader for the neurocritical care unit
  237. Development of an efficient algorithm for quantum transport codes
  238. Development of an implantable Force sensor for orthopedic applications
  239. Development of statistics and contention monitoring unit for PULP
  240. Digital
  241. DigitalUltrasoundHead
  242. Digital Audio Interface for Smart Intensive Computing Triggering
  243. Digital Audio Processor for Cellular Applications
  244. Digital Beamforming for Ultrasound Imaging
  245. Digital Control of a DC/DC Buck Converter
  246. Digital Medical Ultrasound Imaging
  247. Digital Transmitter for Cellular IoT
  248. Digital Transmitter for Mobile Communications
  249. Digitally-Controlled Analog Subtractive Sound Synthesis
  250. EECIS
  251. EEG artifact detection for epilepsy monitoring
  252. EEG artifact detection with machine learning
  253. Edge Computing for Long-Term Wearable Biomedical Systems
  254. Efficient Banded Matrix Multiplication for Quantum Transport Simulations
  255. Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
  256. Efficient Implementation of an Active-Set QP Solver for FPGAs
  257. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  258. Efficient NB-IoT Uplink Design
  259. Efficient Search Design for Hyperdimensional Computing
  260. Efficient Synchronization of Manycore Systems (M/1S)
  261. Efficient TNN Inference on PULP Systems
  262. Efficient TNN compression
  263. Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening
  264. Electrothermal characterization of van der Waals Heterostructures with a partial overlap
  265. Elliptic Curve Accelerator for zkSNARKs
  266. Embedded Artificial Intelligence:Systems And Applications
  267. Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  268. Embedded Gesture Recognition Using Novel Mini Radar Sensors
  269. Embedded Systems and autonomous UAVs
  270. Enabling Efficient Systolic Execution on MemPool (M)
  271. Enabling Standalone Operation
  272. Enabling Standalone Operation for a Mobile Health Platform
  273. Energy-Efficient Brain-Inspired Hyperdimensional Computing
  274. Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
  275. Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
  276. Energy Efficient AXI Interface to Serial Link Physical Layer
  277. Energy Efficient Autonomous UAVs
  278. Energy Efficient Circuits and IoT Systems Group
  279. Energy Efficient Serial Link
  280. Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
  281. Energy Efficient SoCs
  282. Energy Neutral Multi Sensors Wearable Device
  283. Engineering For Kids
  284. Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
  285. Enhancing our DMA Engine with Fault Tolerance
  286. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
  287. EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
  288. EvalEDGE: A 2G Cellular Transceiver FMC
  289. Evaluating An Ultra low Power Vision Node
  290. Evaluating SoA Post-Training Quantization Algorithms
  291. Evaluating memory access pattern specializations in OoO, server-grade cores (M)
  292. Evaluating the RiscV Architecture
  293. Event-Driven Computing
  294. Event-Driven Convolutional Neural Network Modular Accelerator
  295. Event-Driven Vision on an embedded platform
  296. Event-based navigation on autonomous nano-drones
  297. Every individual on the planet should have a real chance to obtain personalized medical therapy
  298. Evolved EDGE Physical Layer Incremental Redundancy Architecture
  299. Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
  300. Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  301. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  302. Exploring Algorithms for Early Seizure Detection
  303. Exploring NAS spaces with C-BRED
  304. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
  305. Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
  306. Exploring schedules for incremental and annealing quantization algorithms
  307. Extend the RI5CY core with priviledge extensions
  308. Extended Verification for Ara
  309. Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
  310. Extending the RISCV backend of LLVM to support PULP Extensions
  311. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
  312. Eye movements
  313. Eye tracking
  314. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  315. FFT-based Convolutional Network Accelerator
  316. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  317. FPGA
  318. FPGA-Based Digital Frontend for 3G Receivers
  319. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
  320. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  321. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  322. FPGA System Design for Computer Vision with Convolutional Neural Networks
  323. FPGA Testbed Implementation for Bluetooth Indoor Positioning
  324. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  325. Fabian Schuiki
  326. Fast Accelerator Context Switch for PULP
  327. Fast Simulation of Manycore Systems (1S)
  328. Fast Wakeup From Deep Sleep State
  329. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  330. Fault Tolerance
  331. Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
  332. Feature Extraction for Speech Recognition (1S)
  333. Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  334. Federico Villani
  335. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  336. Final Presentation
  337. Final Report
  338. Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
  339. Finite Element Simulations of Transistors for Quantum Computing
  340. Finite element modeling of electrochemical random access memory
  341. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
  342. Flexfloat DL Training Framework
  343. Flexible Electronic Systems and Embedded Epidermal Devices
  344. Flexible Front-End Circuit for Biomedical Data Acquisition
  345. Floating-Point Divide & Square Root Unit for Transprecision
  346. Forward error-correction ASIC using GRAND
  347. Frank K. Gürkaynak
  348. Freedom from Interference in Heterogeneous COTS SoCs
  349. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  350. GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
  351. GRAND Hardware Implementation
  352. GSM Voice Capacity Evolution - VAMOS
  353. GUI-developement for an action-cam-based eye tracking device
  354. Glitches Reduce Listening Time of Your iPod
  355. Gomeza old project1
  356. Gomeza old project2
  357. Gomeza old project3
  358. Gomeza old project4
  359. Gomeza old project5
  360. Graph neural networks for epileptic seizure detection
  361. Guillaume Mocquard
  362. HERO: TLB Invalidation
  363. HW/SW Safety and Security
  364. Harald Kröll
  365. Hardware/software co-programming on the Parallella platform
  366. Hardware/software codesign neural decoding algorithm for “neural dust”
  367. Hardware Accelerated Derivative Pricing
  368. Hardware Acceleration
  369. Hardware Accelerator Integration into Embedded Linux
  370. Hardware Accelerator for Model Predictive Controller
  371. Hardware Accelerators for Lossless Quantized Deep Neural Networks
  372. Hardware Constrained Neural Architechture Search
  373. Hardware Support for IDE in Multicore Environment
  374. Heroino: Design of the next CORE-V Microcontroller
  375. Herschmi
  376. Heterogeneous SoCs
  377. High-Resolution, Calibrated Folding ADCs
  378. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  379. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
  380. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
  381. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  382. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  383. High-speed Scene Labeling on FPGA
  384. High-throughput Embedded System For Neurotechnology in collaboration with INI
  385. High Performance Cellular Receivers in Very Advanced CMOS
  386. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  387. High Performance SoCs
  388. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  389. High Speed FPGA Trigger Logic for Particle Physics Experiments
  390. High Throughput Turbo Decoder Design
  391. High performance continous-time Delta-Sigma ADC for biomedical applications
  392. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  393. High resolution, low power Sigma Delta ADC
  394. Huawei Research
  395. Human Intranet
  396. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  397. Hyper-Dimensional Computing Based Predictive Maintenance
  398. Hyper Meccano: Acceleration of Hyperdimensional Computing
  399. Hyperdimensional Computing
  400. Hypervisor Extension for Ariane (M)
  401. IBM A2O Core
  402. IBM Research
  403. IBM Research–Zurich
  404. IP-Based SoC Generation and Configuration (1-3S)
  405. IP-Based SoC Generation and Configuration (1-3S/B)
  406. ISA extensions in the Snitch Processor for Signal Processing (1M)
  407. ISA extensions in the Snitch Processor for Signal Processing (M)
  408. Ibex: Bit-Manipulation Extension
  409. Ibex: FPGA Optimizations
  410. Ibex: Tightly-Coupled Accelerators and ISA Extensions
  411. IcySoC
  412. Image Sensor Interface and Pre-processing
  413. Image and Video Processing
  414. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  415. Implementation of a 2-D model for Li-ion batteries
  416. Implementation of a Coherent Application-Class Multicore System (1-2S)
  417. Implementation of a Heterogeneous System for Image Processing on an FPGA
  418. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  419. Implementation of a NB-IoT Positioning System
  420. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  421. Implementation of an AES Hardware Processing Engine (B/S)
  422. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
  423. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  424. Implementing A Low-Power Sensor Node Network
  425. Implementing Configurable Dual-Core Redundancy
  426. Implementing DSP Instructions in Banshee (1S)
  427. Implementing Hibernation on the ARM Cortex M0
  428. Improved Collision Avoidance for Nano-drones
  429. Improved Reacquisition for the 5G Cellular IoT
  430. Improved State Estimation on PULP-based Nano-UAVs
  431. Improving Cold-Start in Batteryless And Energy Harvesting Systems
  432. Improving Resiliency of Hyperdimensional Computing
  433. Improving Scene Labeling with Hyperspectral Data
  434. Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
  435. Improving datarate and efficiency of ultra low power wearable ultrasound
  436. Improving our Smart Camera System
  437. Indoor Positioning with Bluetooth
  438. Indoor Smart Tracking of Hospital instrumentation
  439. Inductive Charging Circuit for Implantable Devices
  440. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
  441. Influence of the Initial Filament Geometry on the Forming Step in CBRAM
  442. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
  443. Infrared Wake Up Radio
  444. Integrated Devices, Electronics, And Systems
  445. Integrated Information Processing
  446. Integrated silicon photonic structures
  447. Integrated silicon photonic structures-Lumiphase
  448. Integrating Hardware Accelerators into Snitch
  449. Integrating Hardware Accelerators into Snitch (1S)
  450. Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
  451. Integration Of A Smart Vision System
  452. Intelligent Power Management Unit (iPMU)
  453. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  454. Interference Cancellation for EC-GSM-IoT
  455. Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
  456. Interference Cancellation for the cellular Internet of Things
  457. Internet of Things Network Synchronizer
  458. Internet of Things SoC Characterization
  459. Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
  460. Investigation of Metal Diffusion in Oxides for CBRAM Applications
  461. Investigation of Redox Processes in CBRAM
  462. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
  463. Investigation of the source starvation effect in III-V MOSFET
  464. IoT Turbo Decoder
  465. Jammer-Resilient Synchronization for Wireless Communications
  466. Jammer Mitigation Meets Machine Learning
  467. Karim Badawi
  468. Kinetic Energy Harvesting For Autonomous Smart Watches
  469. Knowledge Distillation for Embedded Machine Learning
  471. LLVM and DaCe for Snitch (1-2S)
  472. LTE-Advanced RF Front-end Design in 28nm CMOS Technology
  473. LTE IoT Network Synchronization
  474. Learning Image Compression with Convolutional Networks
  475. Learning Image Decompression with Convolutional Networks
  476. Level Crossing ADC For a Many Channels Neural Recording Interface
  477. Libria
  478. LightProbe
  479. LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
  480. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
  481. LightProbe - CNN-Based-Image-Reconstruction
  482. LightProbe - Design of a High-Speed Optical Link
  483. LightProbe - Frontend Firmware and Control Side Channel
  484. LightProbe - Implementation of compressed-sensing algorithms
  485. LightProbe - Thermal-Power aware on-head Beamforming
  486. LightProbe - Ultracompact Power Supply PCB
  487. LightProbe - WIFI extension (PCB)
  488. Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  489. Linux Driver for fine-grain and low overhead access to on-chip performance counters
  490. Low-Complexity MIMO Detection
  491. Low-Dropout Regulators for Magnetic Resonance Imaging
  492. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  493. Low-Power Time Synchronization for IoT Applications
  494. Low-Resolution 5G Beamforming Codebook Design
  495. Low-power Clock Generation Solutions for 65nm Technology
  496. Low-power Temperature-insensitive Timer
  497. Low-power chip-to-chip communication network
  498. Low-power time synchronization for IoT applications
  499. Low Latency Brain-Machine Interfaces
  500. Low Power Embedded Systems

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