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Showing below up to 500 results in range #1 to #500.

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  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. 3D Turbo Decoder ASIC Realization
  3. 3D Ultrasound Bubble Tracking
  4. 4th Generation Synchronization
  5. 5G Cellular RF Front-end Design in 22nm CMOS Technology
  6. AMZ Driverless Competition Embedded Systems Projects
  7. ASIC
  8. ASIC Design Projects
  9. ASIC Design of a Gaussian Message Passing Processor
  10. ASIC Design of a Sigma Point Processor
  11. ASIC Development of 5G-NR LDPC Decoder
  12. ASIC Implementation of High-Throughput Next Generation Turbo Decoders
  13. ASIC Implementation of Jammer Mitigation
  14. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
  15. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
  16. A Flexible Peripheral System for High-Performance Systems on Chip (M)
  17. A Multiview Synthesis Core in 65 nm CMOS
  18. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
  19. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
  20. A Recurrent Neural Network Speech Recognition Chip
  21. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  22. A Snitch-based Compute Accelerator for HERO
  23. A Snitch-based Compute Accelerator for HERO (M/1-2S)
  24. A Trustworthy Three-Factor Authentication System
  25. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  26. A Unified Compute Kernel Library for Snitch (1-2S)
  27. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  28. A Wearable System To Control Phone And Electronic Device Without Hands
  29. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
  30. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  31. A Wireless Sensor Network for HPC monitoring
  32. A Wireless Sensor Network for a Smart Building Monitor and Control
  33. A Wireless Sensor Network for a Smart LED Lighting control
  34. A computational memory unit using phase-change memory devices
  35. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
  36. Ab-initio Simulation of Strained Thermoelectric Materials
  37. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  38. Acceleration and Transprecision
  39. Accelerator for Boosted Binary Features
  40. Accelerator for Spatio-Temporal Video Filtering
  41. Accelerators for object detection and tracking
  42. Accurate deep learning inference using computational memory
  43. Active-Set QP Solver on FPGA
  44. Adding Linux Support to our DMA Engine (1-2S/B)
  45. Advanced 5G Repetition Combining
  46. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
  47. Aliasing-Free Wavetable Music Synthesizer
  48. All-Digital In-Memory Processing
  49. Ambient RF Energy harvesting for Wireless Sensor Network
  50. An Energy Efficient Brain-Computer Interface using Mr.Wolf
  51. An FPGA-Based Evaluation Platform for Mobile Communications
  52. An FPGA-Based Testbed for 3G Mobile Communications Receivers
  53. An Industrial-grade Bluetooth LE Mesh Network Solution
  54. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  55. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  56. Analog
  57. AnalogInt
  58. Analog Compute-in-Memory Accelerator Interface and Integration
  59. Analog IC Design
  60. Analog Layout Engine
  61. Analog building blocks for mmWave manipulation
  62. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
  63. Andrea Cossettini
  64. Andreas Kurth
  65. Android Software Design
  66. Android reliability governor
  67. Application Specific Frequency Synthesizers (Analog/Digital PLLs)
  68. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
  69. Assessment of novel photovoltaic architectures by circuit simulation
  70. Atretter
  71. Audio
  72. Audio DAC Conversion Jitter Measurement System
  73. Audio Signal Processing
  74. Audio Video Preprocessing In Parallel Ultra Low Power Platform
  75. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  76. Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  77. Automatic unplugging detection for Ultrasound probes
  78. Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
  79. Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
  80. Autonomous Sensing For Trains In The IoT Era
  81. Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
  82. Autonomous Smart Watches: Hardware and Software Desing
  83. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  84. Autonomus Drones With Novel Sensors And Ultra Wide Band
  85. BCI-controlled Drone
  86. BLISS - Battery-Less Identification System for Security
  87. Bandgap voltage reference in 65nm CMOS
  88. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
  89. Baseband Meets CPU
  90. Baseband Processor Development for 4G IoT
  91. Bateryless Heart Rate Monitoring
  92. Battery Tester
  93. Battery indifferent wearable Ultrasound
  94. Beamspace processing for 5G mmWave massive MIMO on GPU
  95. Beat Cadence
  96. Beat DigRF
  97. Benjamin Sporrer
  98. Benjamin Weber
  99. BigPULP: Multicluster Synchronization Extensions
  100. BigPULP: Shared Virtual Memory Multicluster Extensions
  101. Biomedical Circuits, Systems, and Applications
  102. Biomedical System on Chips
  103. Biomedical Systems on Chip
  104. Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  105. Bluetooth Low Energy network with optimized data throughput
  106. Bluetooth Low Energy receiver in 65nm CMOS
  107. Bridging QuantLab with LPDNN
  108. Bringing XNOR-nets (ConvNets) to Silicon
  109. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  110. Brunn test
  111. Build the Fastest 2G Modem Ever
  112. CLIC for the CVA6
  113. CMOS power amplifier for field measurements in MRI systems
  114. CPS Software-Configurable State-Machine
  115. Cell-Free mmWave Massive MIMO Communication
  116. Cell Measurements for the 5G Internet of Things
  117. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  118. Change-based Evaluation of Convolutional Neural Networks
  119. Channel Decoding for TD-HSPA
  120. Channel Estimation and Equalization for LTE Advanced
  121. Channel Estimation for 3GPP TD-SCDMA
  122. Channel Estimation for 5G Cellular IoT and Fast Fading Channels
  123. Channel Estimation for TD-HSPA
  124. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
  125. Characterization techniques for silicon photonics-Lumiphase
  126. Charge-Pump PLL with ring-oscillator based VCO in 65nm CMOS
  127. Charging System for Implantable Electronics
  128. Christoph Keller
  129. Circuits and Systems for Nanoelectrode Array Biosensors
  130. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  131. Coding Guidelines
  132. Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
  133. Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  134. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
  135. Compiler Profiling and Optimizing
  136. Completed
  137. Compressed Sensing Reconstruction on FPGA
  138. Compressed Sensing for Wireless Biosignal Monitoring
  139. Compressed Sensing vs JPEG
  140. Compression of Ultrasound data on FPGA
  141. Compression of iEEG Data
  142. Computation of Phonon Bandstructure in III-V Nanostructures
  143. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
  144. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
  145. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  146. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  147. Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  148. Covariant Feature Detector on Parallel Ultra Low Power Architecture
  149. Creating a HDMI Video Interface for PULP
  150. Cryptography
  151. DC-DC Buck converter in 65nm CMOS
  152. DMA Streaming Co-processor
  153. DaCe on Snitch
  154. Data Augmentation Techniques in Biosignal Classification
  155. Data Interface: SPI to PC Bridge for ASICs
  156. Data Mapping for Unreliable Memories
  157. David J. Mack
  158. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  159. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  160. Deep Convolutional Autoencoder for iEEG Signals
  161. Deep Learning-based Global Local Planner for Autonomous Nano-drones
  162. Deep Learning Projects
  163. Deep Learning for Brain-Computer Interface
  164. Deep Unfolding of Iterative Optimization Algorithms
  165. Deep neural networks for seizure detection
  166. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  167. Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
  168. Design Review
  169. Design and Evaluation of a Small Size Avalanche Beacon
  170. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
  171. Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  172. Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  173. Design and Implementation of a multi-mode multi-master I2C peripheral
  174. Design and Implementation of an Approximate Floating Point Unit
  175. Design and Implementation of ultra low power vision system
  176. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
  177. Design and implementation of the front-end for a portable ionizing radiation detector
  178. Design of Charge-Pump PLL in 22nm for 5G communication applications
  179. Design of MEMs Sensor Interface
  180. Design of Scalable Event-driven Neural-Recording Digital Interface
  181. Design of State Retentive Flip-Flops
  182. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  183. Design of a 25 Gbps SerDes for optical chip-to-chip communication
  184. Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
  185. Design of a Fused Multiply Add Floating Point Unit
  186. Design of a VLIW processor architecture based on RISC-V
  187. Design of an LTE Module for the Internet of Things
  188. Design of an Ultra-Reliable Low-Latency Modem
  189. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
  190. Design of combined Ultrasound and Electromyography systems
  191. Design of low-offset dynamic comparators
  192. Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  193. Design study of tunneling transistors based on a core/shell nanowire structures
  194. Designing a Power Management Unit for PULP SoCs
  195. Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  196. Developing High Efficiency Batteries for Electric Cars
  197. Developing a small portable neutron detector for detecting smuggled nuclear material
  198. Development of a Rockfall Sensor Node
  199. Development of a fingertip blood pressure sensor
  200. Development of a syringe label reader for the neurocritical care unit
  201. Development of an efficient algorithm for quantum transport codes
  202. Development of an implantable Force sensor for orthopedic applications
  203. Digital
  204. DigitalUltrasoundHead
  205. Digital Audio Interface for Smart Intensive Computing Triggering
  206. Digital Audio Processor for Cellular Applications
  207. Digital Beamforming for Ultrasound Imaging
  208. Digital Front End Design & Frequency Offset Estimation for V2X Communications
  209. Digital Medical Ultrasound Imaging
  210. Digital Transmitter for Cellular IoT
  211. Digital Transmitter for Mobile Communications
  212. Digitally-Controlled Analog Subtractive Sound Synthesis
  213. EECIS
  214. EEG artifact detection for epilepsy monitoring
  215. EEG artifact detection with machine learning
  216. Edge Computing for Long-Term Wearable Biomedical Systems
  217. Efficient Implementation of an Active-Set QP Solver for FPGAs
  218. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  219. Efficient NB-IoT Uplink Design
  220. Efficient Search Design for Hyperdimensional Computing
  221. Efficient Synchronization of Manycore Systems (M/1S)
  222. Efficient TNN Inference on PULP Systems
  223. Efficient TNN compression
  224. Electrothermal characterization of van der Waals Heterostructures with a partial overlap
  225. Elliptic Curve Accelerator for zkSNARKs
  226. Embedded Artificial Intelligence:Systems And Applications
  227. Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  228. Embedded Gesture Recognition Using Novel Mini Radar Sensors
  229. Embedded Systems and autonomous UAVs
  230. Enabling Standalone Operation
  231. Enabling Standalone Operation for a Mobile Health Platform
  232. Energy-Efficient Brain-Inspired Hyperdimensional Computing
  233. Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
  234. Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
  235. Energy Efficient Autonomous UAVs
  236. Energy Efficient Circuits and IoT Systems Group
  237. Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
  238. Energy Efficient SoCs
  239. Energy Neutral Multi Sensors Wearable Device
  240. Engineering For Kids
  241. Enhancing our DMA Engine with Fault Tolerance
  242. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
  243. EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
  244. EvalEDGE: A 2G Cellular Transceiver FMC
  245. Evaluating An Ultra low Power Vision Node
  246. Evaluating SoA Post-Training Quantization Algorithms
  247. Evaluating memory access pattern specializations in OoO, server-grade cores (M)
  248. Evaluating the RiscV Architecture
  249. Event-Driven Computing
  250. Event-Driven Convolutional Neural Network Modular Accelerator
  251. Event-Driven Vision on an embedded platform
  252. Every individual on the planet should have a real chance to obtain personalized medical therapy
  253. Evolved EDGE Physical Layer Incremental Redundancy Architecture
  254. Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
  255. Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  256. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  257. Exploring Algorithms for Early Seizure Detection
  258. Exploring Bio Impedance
  259. Exploring NAS spaces with C-BRED
  260. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
  261. Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
  262. Exploring schedules for incremental and annealing quantization algorithms
  263. Extend the RI5CY core with priviledge extensions
  264. Extending the RISCV backend of LLVM to support PULP Extensions
  265. Eye movements
  266. Eye tracking
  267. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  268. FFT-based Convolutional Network Accelerator
  269. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  270. FPGA
  271. FPGA-Based Digital Frontend for 3G Receivers
  272. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
  273. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  274. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  275. FPGA System Design for Computer Vision with Convolutional Neural Networks
  276. FPGA Testbed Implementation for Bluetooth Indoor Positioning
  277. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  278. Fabian Schuiki
  279. Fast Accelerator Context Switch for PULP
  280. Fast Simulation of Manycore Systems (1S)
  281. Fast Wakeup From Deep Sleep State
  282. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  283. Fault Tolerance
  284. Feature Extraction for Speech Recognition (1S)
  285. Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  286. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  287. Final Presentation
  288. Final Report
  289. Finite Element Simulations of Transistors for Quantum Computing
  290. Finite element modeling of electrochemical random access memory
  291. Flexfloat DL Training Framework
  292. Flexible Front-End Circuit for Biomedical Data Acquisition
  293. Floating-Point Divide & Square Root Unit for Transprecision
  294. Fluffy bunny project
  295. Frank K. Gürkaynak
  296. Freedom from Interference in Heterogeneous COTS SoCs
  297. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  298. GSM Voice Capacity Evolution - VAMOS
  299. GUI-developement for an action-cam-based eye tracking device
  300. Glitches Reduce Listening Time of Your iPod
  301. Gomeza old project1
  302. Gomeza old project2
  303. Gomeza old project3
  304. Gomeza old project4
  305. Gomeza old project5
  306. Graph neural networks for epileptic seizure detection
  307. Guillaume Mocquard
  308. HERO: TLB Invalidation
  309. HW/SW Safety and Security
  310. Harald Kröll
  311. Hardware/software co-programming on the Parallella platform
  312. Hardware/software codesign neural decoding algorithm for “neural dust”
  313. Hardware Accelerated Derivative Pricing
  314. Hardware Acceleration
  315. Hardware Accelerator Integration into Embedded Linux
  316. Hardware Accelerator for Model Predictive Controller
  317. Hardware Accelerators for Lossless Quantized Deep Neural Networks
  318. Hardware Constrained Neural Architechture Search
  319. Hardware Support for IDE in Multicore Environment
  320. Heart Rate Detection Algorithm
  321. Heroino: Design of the next CORE-V Microcontroller
  322. Herschmi
  323. Heterogeneous SoCs
  324. High-Performance & V2X Cellular Communications
  325. High-Resolution, Calibrated Folding ADCs
  326. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  327. High-Speed Channel Estimation & Tracking for V2X Communications
  328. High-Speed DigRF-v4 Implementation
  329. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  330. High-Throughput Channel Coding & Decoding for V2X Communications
  331. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  332. High-speed Scene Labeling on FPGA
  333. High-throughput Embedded System For Neurotechnology in collaboration with INI
  334. High Performance Cellular Receivers in Very Advanced CMOS
  335. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  336. High Performance SoCs
  337. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  338. High Speed FPGA Trigger Logic for Particle Physics Experiments
  339. High Throughput Turbo Decoder Design
  340. High performance continous-time Delta-Sigma ADC for biomedical applications
  341. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  342. Huawei Research
  343. Human Intranet
  344. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  345. Hyper-Dimensional Computing Based Predictive Maintenance
  346. Hyper Meccano: Acceleration of Hyperdimensional Computing
  347. Hyperdimensional Computing
  348. Hypervisor Extension for Ariane (M)
  349. IBM A2O Core
  350. IBM Research
  351. IBM Research–Zurich
  352. IP-Based SoC Generation and Configuration (1-3S)
  353. IP-Based SoC Generation and Configuration (1-3S/B)
  354. ISA extensions in the Snitch Processor for Signal Processing (1M)
  355. ISA extensions in the Snitch Processor for Signal Processing (M)
  356. Ibex: Bit-Manipulation Extension
  357. Ibex: FPGA Optimizations
  358. Ibex: Tightly-Coupled Accelerators and ISA Extensions
  359. IcySoC
  360. Image Sensor Interface and Pre-processing
  361. Image and Video Processing
  362. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  363. Implementation of a 2-D model for Li-ion batteries
  364. Implementation of a Heterogeneous System for Image Processing on an FPGA
  365. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  366. Implementation of a NB-IoT Positioning System
  367. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  368. Implementation of an AES Hardware Processing Engine (B/S)
  369. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
  370. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  371. Implementing A Low-Power Sensor Node Network
  372. Implementing DSP Instructions in Banshee (1S)
  373. Implementing Hibernation on the ARM Cortex M0
  374. Improved Collision Avoidance for Nano-drones
  375. Improved Reacquisition for the 5G Cellular IoT
  376. Improved State Estimation on PULP-based Nano-UAVs
  377. Improving Cold-Start in Batteryless And Energy Harvesting Systems
  378. Improving Resiliency of Hyperdimensional Computing
  379. Improving Scene Labeling with Hyperspectral Data
  380. Improving our Smart Camera System
  381. Indoor Positioning with Bluetooth
  382. Indoor Smart Tracking of Hospital instrumentation
  383. Inductive Charging Circuit for Implantable Devices
  384. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
  385. Influence of the Initial Filament Geometry on the Forming Step in CBRAM
  386. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
  387. Infrared Wake Up Radio
  388. Integrated Information Processing
  389. Integrated silicon photonic structures
  390. Integrated silicon photonic structures-Lumiphase
  391. Integrating Hardware Accelerators into Snitch
  392. Integrating Hardware Accelerators into Snitch (1S)
  393. Intelligent Power Management Unit (iPMU)
  394. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  395. Interference Cancellation for EC-GSM-IoT
  396. Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
  397. Interference Cancellation for the cellular Internet of Things
  398. Internet of Things Network Synchronizer
  399. Internet of Things SoC Characterization
  400. Investigation of Metal Diffusion in Oxides for CBRAM Applications
  401. Investigation of Redox Processes in CBRAM
  402. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
  403. Investigation of the source starvation effect in III-V MOSFET
  404. IoT Turbo Decoder
  405. Karim Badawi
  406. Kinetic Energy Harvesting For Autonomous Smart Watches
  407. Knowledge Distillation for Embedded Machine Learning
  408. LAPACK/BLAS for FPGA
  409. LLVM and DaCe for Snitch (1-2S)
  410. LTE-Advanced RF Front-end Design in 28nm CMOS Technology
  411. LTE IoT Network Synchronization
  412. Learning Image Compression with Convolutional Networks
  413. Learning Image Decompression with Convolutional Networks
  414. Level Crossing ADC For a Many Channels Neural Recording Interface
  415. Libria
  416. LightProbe
  417. LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
  418. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
  419. LightProbe - CNN-Based-Image-Reconstruction
  420. LightProbe - Design of a High-Speed Optical Link
  421. LightProbe - Frontend Firmware and Control Side Channel
  422. LightProbe - Implementation of compressed-sensing algorithms
  423. LightProbe - Thermal-Power aware on-head Beamforming
  424. LightProbe - Ultracompact Power Supply PCB
  425. LightProbe - WIFI extension (PCB)
  426. Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  427. Linux Driver for fine-grain and low overhead access to on-chip performance counters
  428. Livestream GUI via USB
  429. Low-Dropout Regulators for Magnetic Resonance Imaging
  430. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  431. Low-Resolution 5G Beamforming Codebook Design
  432. Low-power Clock Generation Solutions for 65nm Technology
  433. Low-power Temperature-insensitive Timer
  434. Low-power chip-to-chip communication network
  435. Low Latency Brain-Machine Interfaces
  436. Low Power Embedded Systems
  437. Low Power Embedded Systems and Wireless Sensors Networks
  438. Low Power Geolocalization And Indoor Localization
  439. Low Power Neural Network For Multi Sensors Wearable Devices
  440. Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
  441. Low Resolution Neural Networks
  442. Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
  443. Machine Learning for extracting Muscle features from Ultrasound raw data
  444. Machine Learning for extracting Muscle features using Ultrasound
  445. Machine Learning for extracting Muscle features using Ultrasound 2
  446. Machine Learning on Ultrasound Images
  447. Main Page
  448. Make Cellular Internet of Things Receivers Smart
  449. Manycore System on FPGA (M/S/G)
  450. Mapping Networks on Reconfigurable Binary Engine Accelerator
  451. MatPHY: An Open-Source Physical Layer Development Framework
  452. Matheus Cavalcante
  453. Matteo Perotti
  454. Matthias Korb
  455. Mattia
  456. Mauro Salomon
  457. MemPool on HERO
  458. MemPool on HERO (1S)
  459. Memory Augmented Neural Networks in Brain-Computer Interfaces
  460. Michael Muehlberghuber
  461. Michael Rogenmoser
  462. Minimal Cost RISC-V core
  463. Minimum Variance Beamforming for Wearable Ultrasound Probes
  464. Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  465. Monocular Vision-based Object Following on Nano-size Robotic Blimp
  466. Moritz Schneider
  467. Multi-Band Receiver Design for LTE Mobile Communication
  468. Multi issue OoO Ariane Backend (M)
  469. Multiuser Equalization and Detection for 3GPP TD-SCDMA
  470. NAND Flash Open Research Platform
  471. NORX - an AEAD algorithm for the CAESAR competition
  472. NVDLA meets PULP
  473. Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
  474. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
  475. Near-Memory Training of Neural Networks
  476. Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
  477. Neural Architecture Search using Reinforcement Learning and Search Space Reduction
  478. Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
  479. Neural Networks Framwork for Embedded Plattforms
  480. Neural Processing
  481. Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  482. New RVV 1.0 Vector Instructions for Ara
  483. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
  484. NextGenChannelDec
  485. Next Generation Channel Decoder
  486. Next Generation Synchronization Signals
  487. Nils Wistoff
  488. Non-binary LDPC Decoder for Deep-Space Optical Communications
  489. Non-blocking Algorithms in Real-Time Operating Systems
  490. Norbert Felber
  491. Novel Metastability Mitigation Technique
  492. Novel Methods for Jammer Mitigation
  493. OTDOA Positioning for LTE Cat-M
  494. On-chip clock synthesizer design and porting
  495. Online Learning of User Features (1S)
  496. OpenRISC SoC for Sensor Applications
  497. Open Power-On Chip Controller Study and Integration
  498. Open Source Baseband Firmware for 2G Cellular Networks
  499. Optimal System Duty Cycling
  500. Optimal System Duty Cycling for a Mobile Health Platform

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