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Showing below up to 394 results in range #501 to #894.

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  1. Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
  2. Interference Cancellation for the cellular Internet of Things
  3. Internet of Things Network Synchronizer
  4. Internet of Things SoC Characterization
  5. Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
  6. Investigation of Metal Diffusion in Oxides for CBRAM Applications
  7. Investigation of Quantization Strategies for Retentive Networks (1S)
  8. Investigation of Redox Processes in CBRAM
  9. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
  10. Investigation of the source starvation effect in III-V MOSFET
  11. IoT Turbo Decoder
  12. Jammer-Resilient Synchronization for Wireless Communications
  13. Jammer Mitigation Meets Machine Learning
  14. Karim Badawi
  15. Kinetic Energy Harvesting For Autonomous Smart Watches
  16. Knowledge Distillation for Embedded Machine Learning
  17. LAPACK/BLAS for FPGA
  18. LLVM and DaCe for Snitch (1-2S)
  19. LTE-Advanced RF Front-end Design in 28nm CMOS Technology
  20. LTE IoT Network Synchronization
  21. Learning Image Compression with Convolutional Networks
  22. Learning Image Decompression with Convolutional Networks
  23. Learning at the Edge with Hardware-Aware Algorithms
  24. Level Crossing ADC For a Many Channels Neural Recording Interface
  25. Libria
  26. LightProbe
  27. LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
  28. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
  29. LightProbe - CNN-Based-Image-Reconstruction
  30. LightProbe - Design of a High-Speed Optical Link
  31. LightProbe - Frontend Firmware and Control Side Channel
  32. LightProbe - Implementation of compressed-sensing algorithms
  33. LightProbe - Thermal-Power aware on-head Beamforming
  34. LightProbe - Ultracompact Power Supply PCB
  35. LightProbe - WIFI extension (PCB)
  36. Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  37. Linux Driver for fine-grain and low overhead access to on-chip performance counters
  38. Low-Complexity MIMO Detection
  39. Low-Dropout Regulators for Magnetic Resonance Imaging
  40. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  41. Low-Power Time Synchronization for IoT Applications
  42. Low-Resolution 5G Beamforming Codebook Design
  43. Low-power Clock Generation Solutions for 65nm Technology
  44. Low-power Temperature-insensitive Timer
  45. Low-power chip-to-chip communication network
  46. Low-power time synchronization for IoT applications
  47. Low Latency Brain-Machine Interfaces
  48. Low Power Embedded Systems
  49. Low Power Embedded Systems and Wireless Sensors Networks
  50. Low Power Geolocalization And Indoor Localization
  51. Low Power Neural Network For Multi Sensors Wearable Devices
  52. Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
  53. Low Precision Ara for ML
  54. Low Resolution Neural Networks
  55. MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
  56. ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
  57. Machine Learning Assisted Direct Synthesis of Passive Networks
  58. Machine Learning for extracting Muscle features from Ultrasound raw data
  59. Machine Learning for extracting Muscle features using Ultrasound
  60. Machine Learning for extracting Muscle features using Ultrasound 2
  61. Machine Learning on Ultrasound Images
  62. Main Page
  63. Make Cellular Internet of Things Receivers Smart
  64. Manycore System on FPGA (M/S/G)
  65. Mapping Networks on Reconfigurable Binary Engine Accelerator
  66. Marco Bertuletti
  67. MatPHY: An Open-Source Physical Layer Development Framework
  68. Matheus Cavalcante
  69. Matteo Perotti
  70. Matthias Korb
  71. Mattia
  72. Mauro Salomon
  73. MemPool on HERO
  74. MemPool on HERO (1S)
  75. Memory Augmented Neural Networks in Brain-Computer Interfaces
  76. Michael Muehlberghuber
  77. Michael Rogenmoser
  78. Minimal Cost RISC-V core
  79. Minimum Variance Beamforming for Wearable Ultrasound Probes
  80. Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  81. Mixed-Signal Circuit Design
  82. Mixed Signal IC Design
  83. Modeling FlooNoC in GVSoC (S/M)
  84. Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
  85. Modular Distributed Data Collection Platform
  86. Modular Frequency-Modulation (FM) Music Synthesizer
  87. Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
  88. Monocular Vision-based Object Following on Nano-size Robotic Blimp
  89. Moritz Schneider
  90. Multi-Band Receiver Design for LTE Mobile Communication
  91. Multi issue OoO Ariane Backend (M)
  92. Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  93. Multiuser Equalization and Detection for 3GPP TD-SCDMA
  94. NAND Flash Open Research Platform
  95. NORX - an AEAD algorithm for the CAESAR competition
  96. NVDLA meets PULP
  97. Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
  98. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
  99. Near-Memory Training of Neural Networks
  100. Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
  101. Network-off-Chip (M)
  102. Network-on-Chip for coherent and non-coherent traffic (M)
  103. Neural Architecture Search using Reinforcement Learning and Search Space Reduction
  104. Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
  105. Neural Networks Framwork for Embedded Plattforms
  106. Neural Processing
  107. Neural Recording Interface and Signal Processing
  108. Neural Recording Interface and Spike Sorting Algorithm
  109. NeuroSoC RISC-V Component (M/1-2S)
  110. Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  111. New RVV 1.0 Vector Instructions for Ara
  112. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
  113. NextGenChannelDec
  114. Next Generation Channel Decoder
  115. Next Generation Synchronization Signals
  116. Nils Wistoff
  117. Noise Figure Measurement for Cryogenic System
  118. Non-binary LDPC Decoder for Deep-Space Optical Communications
  119. Non-blocking Algorithms in Real-Time Operating Systems
  120. Norbert Felber
  121. Novel Metastability Mitigation Technique
  122. Novel Methods for Jammer Mitigation
  123. OTDOA Positioning for LTE Cat-M
  124. Object Detection and Tracking on the Edge
  125. On-Board Software for PULP on a Satellite
  126. On-Device Federated Continual Learning on Nano-Drone Swarms
  127. On-Device Learnable Embeddings for Acoustic Environments
  128. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
  129. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
  130. On-chip clock synthesizer design and porting
  131. On - Device Continual Learning for Seizure Detection on GAP9
  132. Online Learning of User Features (1S)
  133. OpenRISC SoC for Sensor Applications
  134. Open Power-On Chip Controller Study and Integration
  135. Open Source Baseband Firmware for 2G Cellular Networks
  136. Optimal System Duty Cycling
  137. Optimal System Duty Cycling for a Mobile Health Platform
  138. Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
  139. Optimizing the Pipeline in our Floating Point Architectures (1S)
  140. Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
  141. Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
  142. Outdoor Precision Object Tracking for Rockfall Experiments
  143. PREM Intervals and Loop Tiling
  144. PREM Runtime Scheduling Policies
  145. PREM on PULP
  146. PULP
  147. PULP-Shield for Autonomous UAV
  148. PULP Freertos with LLVM
  149. PULP in space - Fault Tolerant PULP System for Critical Space Applications
  150. PULPonFPGA: Hardware L2 Cache
  151. PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  152. PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  153. PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  154. PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  155. PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  156. PULP’s CLIC extensions for fast interrupt handling
  157. PVT Dynamic Adaptation in PULPv3
  158. Palm size chip NMR
  159. Pascal Hager
  160. Passive Radar for UAV Detection using Machine Learning
  161. Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
  162. Peak-to-average power Reduction
  163. Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
  164. Phase-change memory devices for emerging computing paradigms
  165. Philipp Schönle
  166. Physical Implementation of Ara, PULP's Vector Machine (1-2S)
  167. Physical Implementation of ITA (2S)
  168. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  169. Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
  170. Physics is looking for PULP
  171. Pirmin Vogel
  172. Positioning for the cellular Internet of Things
  173. Positioning with Wireless Signals
  174. Power Optimization in Multipliers
  175. Power Saver Mode for Cellular Internet of Things Receivers
  176. Practical Reconfigurable Intelligent Surfaces (RIS)
  177. Prasadar
  178. Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
  179. Precise Ultra-low-power Timer
  180. Predict eye movement through brain activity
  181. Predictable Execution
  182. Predictable Execution on GPU Caches
  183. Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
  184. Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
  185. Probabilistic training algorithms for quantized neural networks
  186. Probing the limits of fake-quantised neural networks
  187. Processing of 3D Micro-tomography data for Lithium Ion Batteries
  188. Project Meetings
  189. Project Plan
  190. Pulse Oximetry Fachpraktikum
  191. Putting Together What Fits Together - GrÆStl
  192. Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
  193. Quantum Transport Modeling of Interband Cascade Lasers (ICL)
  194. Quantum transport in 2D heterostructures
  195. RISC-V base ISA for ultra-low-area cores (2-3G)
  196. RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
  197. RVfplib
  198. Radiation Testing of a PULP ASIC
  199. Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
  200. RazorEDGE: An Evolved EDGE DBB ASIC
  201. Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
  202. Real-Time ECG Contractions Classification
  203. Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
  204. Real-Time Embedded Systems
  205. Real-Time Implementation of Quantum State Identification using an FPGA
  206. Real-Time Motor-Imagery Classification Using Neuromorphic Processor
  207. Real-Time Optical Flow Using Neural Networks
  208. Real-Time Optimization
  209. Real-Time Pedestrian Detection For Privacy Enhancement
  210. Real-Time Stereo to Multiview Conversion
  211. Real-time Linux on RISC-V
  212. Real-time View Synthesis using Image Domain Warping
  213. Real-time eye movement analysis on a tablet computer
  214. Realtime Gaze Tracking on Siracusa
  215. Receiver design for the DigRF 4G high speed serial link
  216. Reconfigurability of SHA-3 candidates
  217. Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication
  218. RedCap-5G for IOT application on prototype taped-out silicon
  219. Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
  220. Research
  221. Resilient Brain-Inspired Hyperdimensional Computing Architectures
  222. Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
  223. Resource Partitioning of Caches
  224. Resource Partitioning of RPC DRAM
  225. Rethinking our Convolutional Network Accelerator Architecture
  226. Robert Balas
  227. Routing 1000s of wires in Network-on-Chips (1-2S/M)
  228. Running Rust on PULP
  229. Runtime partitioning of L1 memory in Mempool (M)
  230. SCMI Support for Power Controller Subsystem
  231. SHAre - An application Specific Instruction Set Processor for SHA-2/3
  232. SSR combined with FREP in LLVM/Clang
  233. SW/HW Predictability and Security
  234. Sandro Belfanti
  235. Satellite Internet of Things
  236. Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
  237. Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
  238. Scan Chain Fault Injection in a PULP SoC (1S)
  239. Scattering Networks for Scene Labeling
  240. Securing Block Ciphers against SCA and SIFA
  241. Self-Learning Drones based on Neural Networks
  242. Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
  243. Self Aware Epilepsy Monitoring
  244. Semi-Custom Digital VLSI for Processing-in-Memory
  245. Sensor Fusion for Rockfall Sensor Node
  246. Serverless Benchmarks on RISC-V (M)
  247. Shared Correlation Accelerator for an RF SoC
  248. Short Range Radars For Biomedical Application
  249. Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
  250. Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
  251. Signal to Noise Ratio Estimation for 3G standards
  252. Simulation of 2D artificial cilia metasurface in COMSOL
  253. Simulation of Li-ion batteries and comparison with experimental data
  254. Simulation of Negative Capacitance Ferroelectric Transistor
  255. Simultaneous Sensing and Communication
  256. Single-Bit-Synapse Spiking Neural System-on-Chip
  257. Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
  258. Skin coupling media characterization for fitnesstracker applications (1 B/S)
  259. SmartRing
  260. Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)
  261. Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
  262. Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)
  263. Smart Meters
  264. Smart Patch For Heath Care And Rehabilitation
  265. Smart Virtual Memory Sharing
  266. Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
  267. Smart e-glasses for concealed recording of EEG signals
  268. Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
  269. Softmax for Transformers (M/1-2S)
  270. Software
  271. Software-Defined Paging in the Snitch Cluster (2-3S)
  272. Spatio-Temporal Video Filtering
  273. Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
  274. Spiking Neural Network for Autonomous Navigation
  275. Spiking Neural Network for Motor Function Decoding Based on Neural Dust
  276. Stand-Alone Edge Computing with GAP8
  277. Standard Cell Compatible Memory Array Design
  278. State-Saving @ NXP
  279. Stefan Lippuner
  280. Stefan Mach
  281. StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
  282. Streaming Integer Extensions for Snitch (M/1-2S)
  283. Streaming Layer Normalization in ITA (M/1-2S)
  284. Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets
  285. Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
  286. Study and Development of Intelligent Capability for Small-Size UAVs
  287. Sub-Noise Floor Channel Tracking
  288. Sub Noise Floor Channel Estimation for the Cellular Internet of Things
  289. Subject specific embeddings for transfer learning in brain-computer interfaces
  290. Successive Approximation Register (SAR) ADC
  291. Successive Interference Cancellation for 3G Downlink
  292. Super Resolution Radar/Imaging at mm-Wave frequencies
  293. Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
  294. Switched Capacitor Based Bandgap-Reference
  295. Synchronisation and Cyclic Prefix Handling For LTE Testbed
  296. Synchronization and Power Control Concepts for 3GPP TD-SCDMA
  297. SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
  298. System Analysis and VLSI Design of NB-IoT Baseband Processing
  299. System Emulation for AR and VR devices
  300. TCNs vs. LSTMs for Embedded Platforms
  301. Taimir Aguacil
  302. Taping a Safer Silicon Implementation of Snitch (M/2-3S)
  303. Tbenz
  304. Telecommunications
  305. Template
  306. Ternary Neural Networks for Face Recognition
  307. Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
  308. Test page
  309. Test project
  310. Testbed Design for Self-sustainable IoT Sensors
  311. Theory, Algorithms, and Hardware for Beyond 5G
  312. Thermal Control of Mobile Devices
  313. Through Wall Radar Imaging using Machine Learning
  314. Time Gain Compensation for Ultrasound Imaging
  315. Time Synchronization for 3G Mobile Communications
  316. Time and Frequency Synchronization in LTE Cat-0 Devices
  317. Timing Channel Mitigations for RISC-V Cores
  318. Tiny CNNs for Ultra-Efficient Object Detection on PULP
  319. Toward Superposition of Brain-Computer Interface Models
  320. Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
  321. Towards Autonomous Navigation for Nano-Blimps
  322. Towards Flexible and Printable Wearables
  323. Towards Formal Verification of the iDMA Engine (1-3S/B)
  324. Towards Online Training of CNNs: Hebbian-Based Deep Learning
  325. Towards Self-Sustainable Unmanned Aerial Vehicles
  326. Towards Self Sustainable UAVs
  327. Towards The Integration of E-skin into Prosthetic Devices
  328. Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
  329. Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
  330. Towards global Brain-Computer Interfaces
  331. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
  332. Trace Debugger for custom RISC-V Core
  333. Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
  334. Transformer Deployment on Heterogeneous Many-Core Systems
  335. Transforming MemPool into a CGRA (M)
  336. Triple-Core PULPissimo
  337. Turbo Decoder Design for High Code Rates
  338. Turbo Equalization for Cellular IoT
  339. Ultra-Efficient Visual Classification on Movidius Myriad2
  340. Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
  341. Ultra-low power processor design
  342. Ultra-low power sampling front-end for acquisition of physiological signals
  343. Ultra-low power transceiver for implantable devices
  344. Ultra-wideband Concurrent Ranging
  345. Ultra Low-Power Oscillator
  346. Ultra Low Power Conversion Circuit For Batteryless Applications
  347. Ultra Low Power Wake Up Radio for Wireless Sensor Network
  348. Ultra low power wearable ultrasound probe
  349. Ultrafast Medical Ultrasound imaging on a GPU
  350. Ultrasound
  351. Ultrasound-EMG combined hand gesture recognition
  352. Ultrasound Doppler system development
  353. Ultrasound High Speed Microbubble Tracking
  354. Ultrasound Low power WiFi with IMX7
  355. Ultrasound based hand gesture recognition
  356. Ultrasound image data recycler
  357. Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
  358. Ultrasound signal processing acceleration with CUDA
  359. Unconventional phase change memory device concepts for in-memory and neuromorphic computin
  360. Using Motion Sensors to Support Indoor Localization
  361. VLSI Design of an Asynchronous LDPC Decoder
  362. VLSI Implementation Polar Decoder using High Level Synthesis
  363. VLSI Implementation of a 5G Ciphering Accelerator
  364. VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
  365. VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
  366. Variability Tolerant Ultra Low Power Cluster
  367. Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
  368. Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
  369. Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
  370. Vector Processor for In-Memory Computing
  371. Versatile HW SW Digital PHY for inter chip communication
  372. Virtual Memory Ara
  373. Visualization of Neural Architecture Search Spaces
  374. Visualizing Functional Microbubbles using Ultrasound Imaging
  375. WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
  376. Wake Up Radio For Energy Efficient Communication System and IC Design
  377. Watchdog Timer for PULP
  378. Weak-strong massive MIMO communication with low-resolution ADCs
  379. Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
  380. Wearable Ultrasound for Artery monitoring
  381. Wearables for Sports and Fitness Tracking
  382. Wearables for Sports and Life Enhancement
  383. Wearables in Fashion
  384. Weekly Reports
  385. Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
  386. Wireless Biomedical Signal Acquisition Device
  387. Wireless Communication Systems for the IoT
  388. Wireless EEG Acquisition and Processing
  389. Wireless In Action Data Streaming in Ski Jumping (1 B/S)
  390. Wireless Sensing With Long Range Comminication (LoRa)
  391. Writing a Hero runtime for EPAC (1-3S/B)
  392. XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
  393. Zephyr RTOS on PULP
  394. Zero Power Touch Sensor and Reciever For Body Communication

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