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Difference between revisions of "StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC"

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[[File:StoneEDGE.jpg|thumb|StoneEDGE die foto.]]
[[File:StoneEDGE.jpg|thumb|StoneEDGE revB1 die photograph.]]

Revision as of 18:26, 2 December 2016

StoneEDGE revB1 die photograph.




Benjamin Weber
Harald Kroell
Stefan Zwicky
David Tschopp
Felix Buergin
Dominik Riha




This chip is the successor of the RazorEDGE chip which implemented 2G Evolved EDGE Level A Digital Baseband (DBB) processing. The stoneEDGE chip implements a complete 2G Evolved EDGE Level A physical layer. It includes up/down-conversion, modulation, analog baseband processing, and DBB processing. In addition, it includes an autonomous incremental redundancy unit supporting the maximum number of concurrent TBFs, which is 32. Furthermore, the chip supports the highest multislot class 45 and the highest DTM multislot class 44. With this setup it is possible to have a maximum downlink data rate of 592.2 kbps and a maximum uplink data rate of 462.6 kbps. Higher layers can access the chip using an SPI interface whereas the analog outputs can be connected to a power amplifier and an antenna.

The chip's name stoneEDGE is based on an analogy between the 2G cellular standard enhancement EDGE and a tool from the prehistoric period Stone Age such as an Acheulean. Both are very old yet durable and useful today.

Well, the real story behind the chip's name is this: The 2G standard is so old it could as well be set in stone.