Difference between revisions of "StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC"
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Revision as of 13:51, 14 November 2017
- Benjamin Weber
- Harald Kroell
- Stefan Zwicky
- David Tschopp
- Felix Buergin
- Jürgen Rogin
- Matthias Korb
- Mauro Salomon
- Dominik Riha
This B version of this chip is the successor of the RazorEDGE chip which implemented 2G Evolved EDGE Level A Digital Baseband (DBB) processing. The stoneEDGE chip implements a complete 2G Evolved EDGE Level A physical layer. It includes up/down-conversion, modulation, analog baseband processing, and DBB processing. In addition, it includes an autonomous incremental redundancy unit supporting the maximum number of concurrent TBFs, which is 32. Furthermore, the chip supports the highest multislot class 45 and the highest DTM multislot class 44. With this setup it is possible to have a maximum downlink data rate of 592.2 kbps and a maximum uplink data rate of 462.6 kbps. Higher layers can access the chip using an SPI interface whereas the analog outputs can be connected to a power amplifier and an antenna.
This successor to the stoneEDGE B1 is the stoneEDGE C1. This revision of the stoneEDGE series improves its predecessor with cellular IoT support. All EC-GSM-IoT physical layer functions are implemented into a single chip leading to a sensitivity of -121.7 dBm. Furthermore, transceiver functionality (RF to digital baseband and vice versa) for LTE Cat-M1 (eMTC) and LTE Cat-NB1 (NB-IoT) are supported as well.
The chip's name stoneEDGE is based on an analogy between the 2G cellular standard enhancement EDGE and a tool from the prehistoric period Stone Age such as an Acheulean. Both are very old yet durable and useful today.
Well, the real story behind the chip's name is this: The 2G standard is so old it could as well be set in stone.
- B. Weber, M. Korb, D. Tschopp, S. Altorfer, J. Rogin, H. Kröll, and Q. Huang, “A SAW-less RF-SoC for cellular IoT supporting EC-GSM-IoT -121.7 dBm sensitivity through EGPRS2A 592 kbps throughput,” in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Sept 2017, pp. 340–343. [Online]. Available: http://dx.doi.org/10.1109/ESSCIRC.2017.8094595