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Successive Interference Cancellation for 3G Downlink

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Performance of the successive interference cancellation multi user detector (SIC-MUD) and the corresponding hardware implementation compared to the traditional linear MMSE equalizer.




Sandro Belfanti


Hasler Foundation




In recent years, a new family of 3G CDMA cellular standards based on time division duplex (TDD), as opposed to the frequency division duplex (FDD) commonly used in 3G systems in Europe, has received increasing attention. A narrow-band version of the UMTS TDD standard, known as low chip rate (LCR) or TD-SCDMA, has been successfully launched in China only few years ago. Unfortunately, in CDMA systems multipath communication channels cause inter-symbol interference (ISI) and consequently destroy the orthogonality of spreading codes, leading to severe multiple access interference (MAI) between the users simultaneously accessing the channel. Hence, digital baseband receiver performance of such systems strongly depends on efficient channel equalization and detection algorithms. Due to the large dimensions of such systems, (optimum) joint maximum-likelihood sequence detection is in general not feasible. Instead, power- and area-efficient linear algorithms, such as linear equalizers, are typically employed.

In this project, the performance and VLSI implementation of successive interference-cancellation (SIC) multiuser detectors (MUD) have been studied, which can outperform linear equalizers in combatting ISI and MAI in CDMA systems. The concept was proven with a corresponding VLSI implementation of a SIC-MUD, which demonstrates that this algorithm is indeed a viable alternative for channel equalization and detection in the TD-SCDMA downlink, producing a noticable gain over traditional linear equalizers at a hardware overhead that is almost negligible when considering the total silicon area of digital baseband tranceiver IC.


  • S. Belfanti, C. Benkeser, K. Badawi, Q. Huang, A. Burg, "Successive Interference Cancellation for 3G Downlink: Algorithm and VLSI Architecture", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, California, USA, 7-10 Oct 2012