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In order to meet these promises, a highly synchronised power-controlled transmission is eminent. Hence, TD-SCDMA utilize a 4-level synchronisation in Time and Frequency (chip, bit, slot and frame levels). In this thesis, fast synchronisation and power control techniques shall be investigated focusing on their performance-complexity tradeoff and their convergence speed. Therefore, Matlab blocks have to be implemented and integrated within our TD-SCDMA simulation chain, followed by implementation in VHDL code, synthesis and design optimization.
 
In order to meet these promises, a highly synchronised power-controlled transmission is eminent. Hence, TD-SCDMA utilize a 4-level synchronisation in Time and Frequency (chip, bit, slot and frame levels). In this thesis, fast synchronisation and power control techniques shall be investigated focusing on their performance-complexity tradeoff and their convergence speed. Therefore, Matlab blocks have to be implemented and integrated within our TD-SCDMA simulation chain, followed by implementation in VHDL code, synthesis and design optimization.
  
===Status: Available ===
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===Status: Obsolete ===
: Looking for 1-2 Semester/Master students
+
: Contact: [[User:Badawi|Karim Badawi]]
: Contact: [http://iis-projects.ee.ethz.ch/index.php/User:Badawi Karim Badawi]
 
  
===Prerequisites===
 
: VLSI I
 
: Interest in Mobile Communications
 
: Matlab and VHDL knowledge
 
 
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===Status: Completed ===
 
: Fall Semester 2014 (sem13h2)
 
: Matthias Baer, Renzo Andri
 
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===Status: In Progress ===
 
: Student A, StudentB
 
: Supervision: [http://iis-projects.ee.ethz.ch/index.php/User:Barandre Andrea Bartolini]
 
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===Character===
 
: 25% Theory
 
: 25% Simulation
 
: 25% Architecture/VHDL
 
: 25% ASIC Implementation
 
 
===Professor===
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] --->
 
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
 
[[Category:Digital]]
 
[[Category:Available]]
 
[[Category:Master Thesis]]
 
 
[[Category:Badawi]]
 
[[Category:Badawi]]
[[Category:Telecommunications]]
 
 
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[[Category:Digital]]
 
[[Category:Analog]]
 
[[Category:TCAD]]
 
[[Category:Nano Electronic]]
 
 
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[[Category:Available]]
 
[[Category:In progress]]
 
[[Category:Completed]]
 
[[Category:Research]]
 
 
TYPE OF WORK
 
[[Category:Semester Thesis]]
 
[[Category:Master Thesis]]
 
[[Category:PhD Thesis]]
 
 
NAMES OF EU/CTI/NT PROJECTS
 
[[Category:UltrasoundToGo]]
 
[[Category:IcySoC]]
 
[[Category:PSocrates]]
 
[[Category:UlpSoC]]
 
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Latest revision as of 10:17, 23 September 2016

Synchronization and Power Control Concepts.jpg

Short Description

TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD nature allows to master asymmetric services more efficiently than other 3G standards. Up- and downlink resources are flexibly assigned according to traffic needs, which is helpful in an environment with increasing data traffic, which tends to be asymmetric (mobile Internet).

In order to meet these promises, a highly synchronised power-controlled transmission is eminent. Hence, TD-SCDMA utilize a 4-level synchronisation in Time and Frequency (chip, bit, slot and frame levels). In this thesis, fast synchronisation and power control techniques shall be investigated focusing on their performance-complexity tradeoff and their convergence speed. Therefore, Matlab blocks have to be implemented and integrated within our TD-SCDMA simulation chain, followed by implementation in VHDL code, synthesis and design optimization.

Status: Obsolete

Contact: Karim Badawi