Difference between revisions of "Telecommunications"
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Revision as of 13:00, 9 February 2015
Supervisors
The following supervisors work in the field of telecommunications. Feel free to contact them if you want to do a project in this field. No pages meet these criteria.
Available Projects
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- Analog building blocks for mmWave manipulation
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
Projects in Progress
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
Completed Projects
- Bluetooth Low Energy receiver in 65nm CMOS
- Advanced 5G Repetition Combining
- Next Generation Synchronization Signals
- Indoor Positioning with Bluetooth
- Turbo Equalization for Cellular IoT
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- Efficient NB-IoT Uplink Design
- Interference Cancellation for EC-GSM-IoT
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Internet of Things SoC Characterization
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- Internet of Things Network Synchronizer
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- 3D Turbo Decoder ASIC Realization
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- Digital Transmitter for Mobile Communications
- FPGA-Based Digital Frontend for 3G Receivers
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- EvalEDGE: A 2G Cellular Transceiver FMC
- RazorEDGE: An Evolved EDGE DBB ASIC
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
- High Throughput Turbo Decoder Design
- Turbo Decoder Design for High Code Rates
- Channel Decoding for TD-HSPA
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Successive Interference Cancellation for 3G Downlink
- Channel Estimation for TD-HSPA
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
