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Timing Channel Mitigations for RISC-V Cores

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Introduction

[timing_channels_intel.png|right|These two timing channel matrices of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical axis) given an input symbol (horizontal axis). The effect of timing mitigation techniques can be clearly observed in the right matrix, where almost no correlation can be observed anymore. Images taken from [1].]]


Project description

The purpose of this project is to get the NVIDIA Deep Learning Accelerator up and running, implement it in a modern ASIC technology node, and compare it against other accelerators in the PULP project. More specifically we would like to see as a result of this project how NVDLA

  • compares against NTX [Schuiki2018], a streaming floating-point accelerator
  • compares against Ara, a vector processor based on the RISC-V Vector extension
  • compares against RI5CY cluster/Ariane [Gautschi2017,Zaruba2018], two scalar RISC-V processors

in terms of performance, area, and power consumption. This includes getting familiar with NVDLA, understanding its programming model, and being able to launch computation on it. Since NVDLA is a large unit, we are also interested to see if and how it can be combined with PULP and what scale such a combination would be beneficial. The difference of scales will make it necessary to consider multiple NTX/Ara/RI5CY clusters/Ariane working in tandem in order to attain meaningful comparisons (such as same-compute, same-area, same-power, same-bandwidth settings).

NVDLA is released as Verilog source code, and all PULP-related sources are in SystemVerilog and VHDL. It is essential that you know or are willing to learn your way around an HDL and ASIC implementation tools (see next section). As a first step we are interested in synthesis results only, but depending on the project's progress we can also consider doing place-and-route to get a feeling how NVDLA behaves in the backend.

Required Skills

To work on this project, you will need:

  • to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) -- having followed the VLSI1 / VLSI2 courses is recommended
  • to have prior knowledge of hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data Analytics" course is recommended

Other skills that you might find useful include:

  • familiarity with git, the UNIX shell, C programming
  • familiarity with basic system security principles

Status: Available

Looking for a Semester Thesis student
Supervision: Michael Schaffner Florian Zaruba Moritz Schneider

Professors

Luca Benini, ETH Zurich
Gernot Heiser, UNSW, Sydney

Practical Details

TBD

Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.

Resources

  • [arianeGit] Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set [2]
  • [Zaruba2018] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [3]
  • [data61timing] Gernot Heiser, et al. "Mitigating microarchitectural timing channels with hardware-provided operations" [4]
  • [Ge2018a] Ge, Qian et al. "No Security Without Time Protection: We Need a New Hardware-Software Contract." [5]
  • [Ge2018b] Ge, Qian et al. "Time Protection: the Missing OS Abstraction." [6]

Links

  • The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [7]
  • The IIS/DZ coding guidelines [8]