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Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)

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Status: Available


Almost all systems developed at IIS are using AXI (Advanced eXtensible Interface) as their main on-chip interface. So far we have relied on an extensive AXI verification infrastructure based on behavioral SystemVerilog code. With the advent of large high-performance scientific computing and machine-learning systems (Occamy, Mempool) simulation time increased massively making it in many cases even impossible to run the required simulations.

Verilator is a fully open-source simulation environment allowing synthesizable SystemVerilog code to be translated into natively machine-executable code. This allows verilated designs to be simulated at speeds comparable to FPGAs.


You will develop a set of testbench IPs to simulate AXI-based systems and IPs using Verilator. This includes:

  • An AXI manager unit to drive a bus using an API and/or file-based stimuli
  • An AXI subordinate device using real memory
  • A randomized version of the above IPs.

You will have the chance to benchmark, optimize, and improve your testbenches simulating a large manycore system running real machine learning workloads (or booting Linux!).


  • 20% Planning and design of the test environment
  • 40% Implementing a C++ testbench
  • 20% Verification of / Improving the testbench
  • 20% Benchmark and optimize the simulation speed of a large manycore system.


  • Interest in memory systems
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Knowledge of C/C++
  • Preferred: Knowledge of AXI4
  • Preferred: Experience with Verilator