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Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)

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Revision as of 12:57, 27 October 2022 by Smazzola (talk | contribs) (Project Description)
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Overview

Status: In Progress

Character

  • 5% Literature/architecture review
  • 65% RTL implementation
  • 30% Evaluation

Prerequisites

  • Experience with RTL design and evaluation

Introduction

At IIS we design, develop, and maintain the de-facto only usable free and open-source AMBA AXI4 implementation. So far we focused on creating synthesizable interconnect IPs and non-synthesizable verification and monitoring IPs. This approach works well to create the systems (and implement them) and do most of the evaluation in simulation. It no longer works once the need arises: 1. to evaluate (large) systems on FPGAs and/or ASICs. 2. to have a synthesizable fully configurable memory system. 3. to monitor key figures of merit online and in-system.

To summarize; we need platform-independent, synthesizable, low-overhead AXI4 monitor and throttling unit(s).

Project Description

The following are the milestones that we expect to achieve throughout the project:

  • Familiarize yourself with the AXI4 protocol and the PULP AXI4 implementation
  • Create an extensive list of key figures of merit to monitor and compile a list of events required to track them.
  • Design and implement such an AXI4 event unit, evaluate it to prove it is working, and synthesize it in an ASIC technology to investigate the area/timing/power overheads.

Stretch Goals Should the above milestones be reached earlier than expected and you are motivated to do further work, we propose the following stretch goals to aim for:

  • Create a performance counter unit allowing you to track your events.
  • Create a throttling unit that limits the number of outstanding transfers downstream as well as introduces a varying amount of per-channel delay.