http://iis-projects.ee.ethz.ch/index.php?title=Training_and_Deploying_Next-Generation_Quantized_Neural_Networks_on_Microcontrollers&feed=atom&action=historyTraining and Deploying Next-Generation Quantized Neural Networks on Microcontrollers - Revision history2024-03-28T19:58:09ZRevision history for this page on the wikiMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Training_and_Deploying_Next-Generation_Quantized_Neural_Networks_on_Microcontrollers&diff=7098&oldid=prevGeorg: Georg moved page Training and Deploying Next-Generation Neural Networks on Microcontrollers to Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers2021-10-29T09:32:40Z<p>Georg moved page <a href="/index.php?title=Training_and_Deploying_Next-Generation_Neural_Networks_on_Microcontrollers" class="mw-redirect" title="Training and Deploying Next-Generation Neural Networks on Microcontrollers">Training and Deploying Next-Generation Neural Networks on Microcontrollers</a> to <a href="/index.php?title=Training_and_Deploying_Next-Generation_Quantized_Neural_Networks_on_Microcontrollers" title="Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers">Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers</a></p>
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</td></tr></table>Georghttp://iis-projects.ee.ethz.ch/index.php?title=Training_and_Deploying_Next-Generation_Quantized_Neural_Networks_on_Microcontrollers&diff=6680&oldid=prevGeorg: Created page with "==Description== The design and deployment of highly efficient neural networks (NNs) to be executed on microcontroller-class systems (MCUs) has seen intense attention from the..."2021-07-16T14:56:58Z<p>Created page with "==Description== The design and deployment of highly efficient neural networks (NNs) to be executed on microcontroller-class systems (MCUs) has seen intense attention from the..."</p>
<p><b>New page</b></p><div>==Description==<br />
The design and deployment of highly efficient neural networks (NNs) to be executed on microcontroller-class systems (MCUs) has seen intense attention from the research community in recent times, with the current state of the art being represented by MCUNet (see references). Due to the architectural limitations of commodity MCUs, exploiting sub-byte formats for a better model size-accuracy tradeoff has seen only limited attention - while many approaches to network design and quantization have been proposed, only few publications present a flow to map these networks to real systems.<br />
<br />
The PULP family of MCUs developed at IIS has hardware support for ultra-low-precision (down to 2 bits) SIMD arithmetic, which was introduced with the express goal of supporting such networks. Furthermore, we have been developing QuantLab, a framework for training quantized NNs and have recently created a prototype flow for automatically integerizing arbitrary precision networks.<br />
<br />
The goal of this project is to leverage these existing tools to train and deploy mixed-precision networks on PULP-based systems. More precisely, in this project, you will:<br />
<br />
#Select one or more suitable state-of-the-art networks to target a given PULP platform specification - e.g. MCUNet<br />
#(Re)train this network with different per-layer precisions, using approaches from literature or developed yourself to determine the precision for each layer<br />
#Integerize the mixed-precision network for execution on PULP using our newly developed pipeline<br />
#Compare the accuracy-latency-model size tradeoff to the baseline 8-bit model.<br />
<br />
A detailed task description and project plan will be uploaded soon, if you are interested in this project and/or have any questions, please do not hesitate to contact us!<br />
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===Status: Available ===<br />
Looking for 1-2 students for a Semester project, or potentially a single student for a Master's thesis. <br />
<br />
: Supervision: [[:User:Georg|Georg Rutishauser]], [[:User:Scheremo|Moritz Scherer]]<br />
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===Prerequisites===<br />
* Machine Learning<br />
* Python<br />
* C<br />
===Character===<br />
: 25% Theory<br />
: 75% Implementation<br />
<br />
===Literature===<br />
* [https://arxiv.org/abs/2007.10319] J. Lin et al., MCUNet: Tiny Deep Learning on IoT Devices<br />
* [https://arxiv.org/abs/1905.13082] M. Rusci et al., Memory-Driven Mixed Low Precision Quantization For Enabling Deep Network Inference On Microcontrollers<br />
<br />
<br />
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===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
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* description of the most promising architectures, and argumentation on the decision taken (as part of the report)<br />
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===Practical Details===<br />
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