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Difference between revisions of "Triple-Core PULPissimo"

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[[Category:Semester Thesis]]
[[Category:Semester Thesis]]
= Overview =
= Overview =

Latest revision as of 07:49, 21 June 2022


Status: Reserved


The miniaturization of increasingly complex integrated circuits (ICs) is coupled with a reduction of their noise margin, which makes such circuits more and more exposed to faults and failures. The problem is even more accentuated in critical applications, such as for satellites in space or electronics in particle accelerators, required to capture sensor output. While space electronics are exposed to cosmic rays, particle accelerators experience a far higher level of radiation, especially considering high energy particles capable of triggering transient faults (soft errors). Faster clocks increase the probability of signal spikes being captured by sequential elements, taking the system into a faulty state. While some fault tolerance schemes utilize Triple Modular Redundancy (TMR) at gate level to ensure reliability, other schemes replicate entire blocks or processor cores, or only add Error Correcting Codes (ECC) to data stored in memory.


The core goal of the project is to design and tape out a triple-core PULPissimo SoC with ECC memory. This includes adapting the PULPissimo SoC to include three cores with a TMR voting architecture, as well as ECC encoders and decoders to ensure Single Error Correction, Double Error Detection (SECDED) protection in each memory word. Furthermore, the design should be implemented in TSMC 28nm HPC+ for a tapeout.


  • 10% Literature Review
  • 80% Hardware Design
  • 10% Evaluation & Documentation


  • Strong interest in computer architecture
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • VLSI 2 attendance or previous attendance of a similar course is mandatory