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Line 20: Line 20:
: Supervision: [[:User:Mluisier | Mathieu Luisier]]
: Supervision: [[:User:Mluisier | Mathieu Luisier]]
: 40% Theory, Algorithms, and Simulation
: 20% Architectural Design
: 40% HDL Implementation

Revision as of 11:43, 13 November 2018

Turbo Equalizer Block Diagram

Short Description

Turbo equalization is a well-known approach to improve the overall performance of a wireless communication system. The underlying principle is to feed back soft information from the channel decoder to the channel equalizer and channel estimator in an iterative manner. However, due to the iterative nature of Turbo equalization there are severe challenges to meet latency requirements in almost all communication standards which is one of the reasons why Turbo equalization is found only seldom in practical receiver implementations today.

With the focus of communication systems being partly shifted from ever increasing throughput requirements to low-throughput, long-range communication systems in order to enable cellular IoT (Internet of Things), the upcoming communication standards such as LTE Cat-M2 heavily rely on the re-transmissions of the same data blocks. This represents an unique opportunity: The iterative Turbo equalization can already be performed in parallel to the actual data transmission. Thus, any additional latency contribution can be completely hidden making Turbo equalization a viable solution in practical communication systems.

Your first task in this project is to upgrade the available Matlab-based LTE-simulation environment to support a standard Turbo equalization algorithm. In a next step this algorithm needs to be adapted towards the LTE Cat-M2 physical communication channels which support codeword repetitions. In the next phase an architectural concept for a hardware implementation will be developed that especially needs to consider the synchronization of the channel equalizer and the channel decoder. Finally, you will port the algorithm to an HDL implementation and synthesize it either towards an FPGA or an ASIC implementation in order to analyze the hardware complexity of the developed algorithm.

Status: Completed

Contact: Matthias Korb


Qiuting Huang

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