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My research interest involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.
 
My research interest involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.
 
   
 
   
My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.      
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My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.
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==Contact==
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* Office: ETZ J89
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* E-Mail: [mailto:aottaviano@iis.ee.ethz.ch aottaviano@iis.ee.ethz.ch]
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* Phone: +41 44 632 57 45   
  
 
==Projects==
 
==Projects==

Revision as of 08:49, 6 January 2022

Alessandro Ottaviano

My research interest involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.

My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.

Contact

Projects

Available Projects


Projects In Progress


Completed Projects