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=Alessandro Ottaviano=
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[[File:aottaviano.jpg|frameless|right|180px]]
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My research involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.
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My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.
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==Contact==
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* Office: ETZ J89
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* E-Mail: [mailto:aottaviano@iis.ee.ethz.ch aottaviano@iis.ee.ethz.ch]
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* Phone: +41 44 632 57 45   
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==Interests==
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* Processor/SoC Design
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* FPGA emulation and ASIC Design
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* Real-Time/Predictability
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* Operating Systems/Compilers
  
 
==Projects==
 
==Projects==
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Latest revision as of 09:28, 6 January 2022

Aottaviano.jpg

My research involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.

My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.

Contact

Interests

  • Processor/SoC Design
  • FPGA emulation and ASIC Design
  • Real-Time/Predictability
  • Operating Systems/Compilers

Projects

Available Projects


Projects In Progress


Completed Projects