Difference between revisions of "User:Aottaviano"
(Created page with "=Alessandro Ottaviano= ==Projects== ===Available Projects=== <DynamicPageList> category = Available category = Aottaviano suppresserrors=true </DynamicPageList> ===Projects...")
|Line 1:||Line 1:|
Revision as of 09:42, 6 January 2022
My research interest involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.
My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.
- CLIC for the CVA6
- Fast Accelerator Context Switch for PULP
- SCMI Support for Power Controller Subsystem
- Non-blocking Algorithms in Real-Time Operating Systems
Projects In Progress
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Efficient Synchronization of Manycore Systems (M/1S)