Difference between revisions of "User:Aottaviano"
From iis-projects
Aottaviano (talk | contribs) |
Aottaviano (talk | contribs) |
||
| Line 11: | Line 11: | ||
==Interests== | ==Interests== | ||
| − | * Processor | + | * Processor/SoC Design |
| − | |||
* FPGA emulation and ASIC Design | * FPGA emulation and ASIC Design | ||
* Real-Time/Predictability | * Real-Time/Predictability | ||
Revision as of 09:51, 6 January 2022
Contents
Alessandro Ottaviano
My research interest involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.
My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.
Contact
- Office: ETZ J89
- E-Mail: aottaviano@iis.ee.ethz.ch
- Phone: +41 44 632 57 45
Interests
- Processor/SoC Design
- FPGA emulation and ASIC Design
- Real-Time/Predictability
- Operating Systems/Compilers
Projects
Available Projects
- CLIC for the CVA6
- Fast Accelerator Context Switch for PULP
- SCMI Support for Power Controller Subsystem
- Non-blocking Algorithms in Real-Time Operating Systems
Projects In Progress
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Efficient Synchronization of Manycore Systems (M/1S)
