My research interest involves the world of Integrated Circuits and Computer Architecture, especially VLSI FPGA/ASIC design and Real Time Predictable embedded systems.
My work leverages the interface between SW (Real Time Operative Systems - RTOS and C systems programming) and HW (HDL design, FPGA emulation, gate-level ASIC design) towards the implementation of General Purpose computing platforms on silicon.
- PULP Freertos with LLVM
- Zephyr RTOS on PULP
- CLIC for the CVA6
- Fast Accelerator Context Switch for PULP
- Non-blocking Algorithms in Real-Time Operating Systems
Projects In Progress
- Development of statistics and contention monitoring unit for PULP
- SCMI Support for Power Controller Subsystem
- Efficient Synchronization of Manycore Systems (M/1S)
- A Unified Compute Kernel Library for Snitch (1-2S)
- PULP’s CLIC extensions for fast interrupt handling
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)