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==Interests==
 
==Interests==
My research focus is on deploying Machine Learning Workloads on High-Performance Computing systems. Specifically I am interested in HW/SW Co-design of DNN Training algorithms as well as low-precision floating point DNN training. I have also previously worked onML Hardware Accelerator for edge applications.
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My research focuses on interconnects for on-chip and off-chip communication in HPC Systems. Specifically, I am currently working on Network-on-Chips (NoCs) to enable scaling out to manycore systems. Further, I have also worked on a Die-to-Die link for chiplet-based systems.
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Previously, I also deployed Machine Learning Workloads on High-Performance Computing systems and worked on ML Hardware Accelerator for edge applications.
  
  
  
 
==Contact Information==
 
==Contact Information==
* '''Office''': ETZ J 76.2
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* '''Office''': OAT U21
 
* '''e-mail''': [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
 
* '''e-mail''': [mailto:fischeti@iis.ee.ethz.ch fischeti@iis.ee.ethz.ch]
* '''phone''': +41 44 632 59 12
 
 
* '''www''': [https://iis.ee.ethz.ch/people/person-detail.MjE3MzI0.TGlzdC8zOTg3LDk5MDE4ODk4MA==.html IIS Homepage]
 
* '''www''': [https://iis.ee.ethz.ch/people/person-detail.MjE3MzI0.TGlzdC8zOTg3LDk5MDE4ODk4MA==.html IIS Homepage]
  
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[[Category: Supervisors]]
 
[[Category: Supervisors]]
 
[[Category: Digital]]
 
[[Category: Digital]]
[[Category: Deep Learning Acceleration]]
 
[[Category: Hardware Acceleration]]
 
  
 
==Projects In Progress==
 
==Projects In Progress==
 
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<DynamicPageList>
 
supresserrors = true
 
supresserrors = true
category = Available
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category = In Progress
 
category = Fischeti
 
category = Fischeti
 
</DynamicPageList>
 
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Latest revision as of 16:00, 3 November 2023

Tim Fischer.jpeg

Tim Fischer

I received my Bachelor's degree in Information Technology and Electrical Engineering from Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland in 2018 and my Master's degree in April 2020. After that, I started as a PhD Student in the digital circuits and systems group of Prof. Dr. L. Benini

Interests

My research focuses on interconnects for on-chip and off-chip communication in HPC Systems. Specifically, I am currently working on Network-on-Chips (NoCs) to enable scaling out to manycore systems. Further, I have also worked on a Die-to-Die link for chiplet-based systems.

Previously, I also deployed Machine Learning Workloads on High-Performance Computing systems and worked on ML Hardware Accelerator for edge applications.


Contact Information

Available Projects


Projects In Progress

No pages meet these criteria.

Completed Projects