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| + | Luca Bertaccini received a Master's degree in Electronic Engineering from the University of Bologna in 2020. He is currently pursuing a PhD at the Integrated Systems Laboratory (IIS) of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. His research is mainly focused on hardware accelerators for ultra-?low-power platforms. | ||
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==Luca Bertaccini -- Contact Information== | ==Luca Bertaccini -- Contact Information== | ||
* '''Office''': ETZ J 78 | * '''Office''': ETZ J 78 | ||
Revision as of 01:30, 1 November 2020
Luca Bertaccini received a Master's degree in Electronic Engineering from the University of Bologna in 2020. He is currently pursuing a PhD at the Integrated Systems Laboratory (IIS) of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. His research is mainly focused on hardware accelerators for ultra-?low-power platforms.
Luca Bertaccini -- Contact Information
- Office: ETZ J 78
- e-mail: lbertaccini@iis.ee.ethz.ch
- www: IIS Homepage
Interests
- Hardware Acceleration
- Digital ASIC Design
- Low-Power Design
Available Projects
- Extending our FPU with Internal High-Precision Accumulation (M)
- Hardware Exploration of Shared-Exponent MiniFloats (M)
Projects in Progress
Completed Projects
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Smart Meters
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
