Difference between revisions of "User:Lbertaccini"

Revision as of 12:21, 19 November 2021

I received my Master's degree in Electronic Engineering from the University of Bologna in 2020. I am currently pursuing a PhD at the Integrated Systems Laboratory (IIS) of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. My research interests include:

• Hardware accelerators (Floating-Point Unit, FFT accelerators, ML accelerators)
• Manycore systems
• Energy-Efficient SoCs
• Heterogenous architecures

Luca Bertaccini -- Contact Information

• Office: ETZ J 78
• e-mail: lbertaccini@iis.ee.ethz.ch
• www: IIS Homepage

Interests

• Hardware Acceleration
• Digital ASIC Design
• Low-Power Design

Available Projects

• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)

Projects in Progress

• Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)

Completed Projects

• Smart Meters
• Optimizing the Pipeline in our Floating Point Architectures (1S)
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)