Matteo Perotti

Matteo Perotti

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I am interested in everything is hardware, from highly efficient low-power implementations to high-performance vector processors.

I mainly work on RISC-​V architectures, and I am secretly in love with the SW-​side of the world.

I come from Turin, Italy, where I received my Bachelor's and Master's Degrees from Politecnico di Torino.

Interests

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• Computer and System Architectures
• HPC and Vector Processors
• RISC-V ISA
• Code-Size optimizations

Contact Information

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• e-mail: mperotti@iis.ee.ethz.ch
• phone: +41 44 632 05 25
• office: OAT U21

Projects

Available Projects

• Big Data Analytics Benchmarks for Ara
• Virtual Memory Ara
• Extended Verification for Ara
• Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
• New RVV 1.0 Vector Instructions for Ara
• RVfplib

Projects In Progress

• Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)

Completed Projects

• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
• Multi issue OoO Ariane Backend (M)
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)