I am is interested in everything is HW, from highly efficient low-power implementations to high-performance vector processors.
I mainly work with RISC-V architectures, but I am also secretly in love with the SW-side of the world.
I come from Turin, Italy, where I received my Bachelor's and Master's Degrees from Politecnico di Torino.
- Computer and System Architectures
- HPC and Vector Processors
- RISC-V ISA
- Code-Size optimizations
- e-mail: firstname.lastname@example.org
- phone: +41 44 632 05 25
- office: ETZ J85
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- New RVV 1.0 Vector Instructions for Ara
Projects In Progress