I am interested in everything is hardware, from highly efficient low-power implementations to high-performance vector processors.
I mainly work on RISC-V architectures, and I am secretly in love with the SW-side of the world.
I come from Turin, Italy, where I received my Bachelor's and Master's Degrees from Politecnico di Torino.
- Computer and System Architectures
- HPC and Vector Processors
- RISC-V ISA
- Code-Size optimizations
- e-mail: email@example.com
- phone: +41 44 632 05 25
- office: OAT U21
- Big Data Analytics Benchmarks for Ara
- Virtual Memory Ara
- Extended Verification for Ara
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- New RVV 1.0 Vector Instructions for Ara
Projects In Progress