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(Pasquale Davide Schiavone)
(Available projects)
 
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== '''Available projects''' ==
 
== '''Available projects''' ==
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* [[MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.]] (semester/master thesis)
 
* [[Heroino: Design of the next CORE-V Microcontroller]] (semester/master thesis)
 
* [[Heroino: Design of the next CORE-V Microcontroller]] (semester/master thesis)
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* [[Design of Scalable Event-driven Neural-Recording Digital Interface]] (semester/master thesis)
 
* [[Design of Scalable Event-driven Neural-Recording Digital Interface]] (semester/master thesis)
 
* [[Design of Scalable Event-driven Neural-Recording Digital Interface]] (semester/master thesis)
 
* If you have your personal idea, you can also contact me for projects!
 
* If you have your personal idea, you can also contact me for projects!

Latest revision as of 16:22, 15 August 2022

Pasquale Davide Schiavone

Pasquale Davide Schiavone is a PostDoc at the Embedded System Laboratory at EPF Lausanne, and former PhD student at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. He obtained a BSc. and a MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016 respectively. His main research focus is on low-power energy-efficient computer architectures for Internet-Of-Things systems and brain-machine interfaces through EEG and neural action potential signals.

Interests

  • Computer and System Architecture
  • Digital ASIC Design
  • Embedded systems
  • Heterogeneous multicore architectures for energy-efficient and low-power embedded systems
  • Brain-Machine interface


Available projects

Completed projects

Contact Information