User:Smazzola

Available Projects

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Projects In Progress

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Completed Projects

• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
• Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
• Exploring NAS spaces with C-BRED
• Bandwidth Efficient NEureka
• Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
• Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
• Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
• Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
• Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
• Resource Partitioning of Caches
• Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
• Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
• Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
• Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
• Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
• Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
• Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
• Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
• Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
• Enabling Efficient Systolic Execution on MemPool (M)
• Network-off-Chip (M)
• Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
• Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
• Audio Visual Speech Recognition (1S/1M)
• Audio Visual Speech Separation (1S/1M)
• Evaluating SoA Post-Training Quantization Algorithms
• Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
• Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
• A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
• Smart e-glasses for concealed recording of EEG signals
• Transformer Deployment on Heterogeneous Many-Core Systems
• Smart Meters
• Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
• Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
• Wireless EEG Acquisition and Processing
• Development of statistics and contention monitoring unit for PULP
• Implementing Configurable Dual-Core Redundancy
• Running Rust on PULP
• Ultrasound based hand gesture recognition
• Optimizing the Pipeline in our Floating Point Architectures (1S)
• Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
• Mapping Networks on Reconfigurable Binary Engine Accelerator
• Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
• Neural Architecture Search using Reinforcement Learning and Search Space Reduction
• Bridging QuantLab with LPDNN
• Bluetooth Low Energy receiver in 65nm CMOS
• Novel Metastability Mitigation Technique
• Analog Compute-in-Memory Accelerator Interface and Integration
• Wearables in Fashion
• Outdoor Precision Object Tracking for Rockfall Experiments
• Autonomous Sensing For Trains In The IoT Era
• CLIC for the CVA6
• Flexfloat DL Training Framework
• Online Learning of User Features (1S)
• Feature Extraction for Speech Recognition (1S)
• SCMI Support for Power Controller Subsystem
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
• Implementing DSP Instructions in Banshee (1S)
• Streaming Integer Extensions for Snitch (M/1-2S)
• Efficient Synchronization of Manycore Systems (M/1S)
• Design of combined Ultrasound and Electromyography systems
• Designing a Power Management Unit for PULP SoCs
• A Unified Compute Kernel Library for Snitch (1-2S)
• PULP’s CLIC extensions for fast interrupt handling
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
• Adding Linux Support to our DMA Engine (1-2S/B)
• Triple-Core PULPissimo
• Watchdog Timer for PULP
• Hypervisor Extension for Ariane (M)
• Advanced 5G Repetition Combining
• Next Generation Synchronization Signals
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
• Improved State Estimation on PULP-based Nano-UAVs
• Ultra low power wearable ultrasound probe
• Machine Learning for extracting Muscle features using Ultrasound 2
• Hardware Constrained Neural Architechture Search
• Implementation of an AES Hardware Processing Engine (B/S)
• Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
• Transforming MemPool into a CGRA (M)
• Multi issue OoO Ariane Backend (M)
• Exploring schedules for incremental and annealing quantization algorithms
• Memory Augmented Neural Networks in Brain-Computer Interfaces
• Hyper-Dimensional Computing Based Predictive Maintenance
• Low Latency Brain-Machine Interfaces
• Ultrasound Low power WiFi with IMX7
• Ultrasound signal processing acceleration with CUDA
• Minimum Variance Beamforming for Wearable Ultrasound Probes
• Machine Learning for extracting Muscle features using Ultrasound
• Compression of Ultrasound data on FPGA
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• LLVM and DaCe for Snitch (1-2S)
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• Manycore System on FPGA (M/S/G)
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
• LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
• Time Gain Compensation for Ultrasound Imaging
• Neural Networks Framwork for Embedded Plattforms
• Securing Block Ciphers against SCA and SIFA
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• ISA extensions in the Snitch Processor for Signal Processing (M)
• Design and Evaluation of a Small Size Avalanche Beacon
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
• MemPool on HERO (1S)
• NVDLA meets PULP
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
• A Recurrent Neural Network Speech Recognition Chip
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
• Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
• Deep Convolutional Autoencoder for iEEG Signals
• Ibex: FPGA Optimizations
• Ibex: Bit-Manipulation Extension
• Floating-Point Divide & Square Root Unit for Transprecision
• Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
• TCNs vs. LSTMs for Embedded Platforms
• An Energy Efficient Brain-Computer Interface using Mr.Wolf
• Timing Channel Mitigations for RISC-V Cores
• A computational memory unit using phase-change memory devices
• Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
• Real-Time ECG Contractions Classification
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
• Exploring Algorithms for Early Seizure Detection
• HERO: TLB Invalidation
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
• Indoor Positioning with Bluetooth
• Improving Resiliency of Hyperdimensional Computing
• Toward Superposition of Brain-Computer Interface Models
• Predictable Execution on GPU Caches
• Freedom from Interference in Heterogeneous COTS SoCs
• Deep Learning for Brain-Computer Interface
• LightProbe - WIFI extension (PCB)
• Digital Audio Interface for Smart Intensive Computing Triggering
• Trace Debugger for custom RISC-V Core
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
• Turbo Equalization for Cellular IoT
• Shared Correlation Accelerator for an RF SoC
• IoT Turbo Decoder
• BigPULP: Shared Virtual Memory Multicluster Extensions
• Sensor Fusion for Rockfall Sensor Node
• Development of a Rockfall Sensor Node
• FPGA Optimizations of Dense Binary Hyperdimensional Computing
• Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
• Intelligent Power Management Unit (iPMU)
• Ultrafast Medical Ultrasound imaging on a GPU
• LightProbe - Implementation of compressed-sensing algorithms
• A Wireless Sensor Network for a Smart Building Monitor and Control
• Creating a HDMI Video Interface for PULP
• Standard Cell Compatible Memory Array Design
• Efficient NB-IoT Uplink Design
• Interference Cancellation for EC-GSM-IoT
• A Wireless Sensor Network for HPC monitoring
• Towards Self-Sustainable Unmanned Aerial Vehicles
• Study and Development of Intelligent Capability for Small-Size UAVs
• Towards Autonomous Navigation for Nano-Blimps
• PULP-Shield for Autonomous UAV
• Self-Learning Drones based on Neural Networks
• BigPULP: Multicluster Synchronization Extensions
• Smart Virtual Memory Sharing
• Sub Noise Floor Channel Estimation for the Cellular Internet of Things
• Hardware Accelerated Derivative Pricing
• Internet of Things SoC Characterization
• VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
• Glitches Reduce Listening Time of Your iPod
• Internet of Things Network Synchronizer
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
• Accelerator for Boosted Binary Features
• Accelerator for Spatio-Temporal Video Filtering
• WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
• System Analysis and VLSI Design of NB-IoT Baseband Processing
• High-speed Scene Labeling on FPGA
• Learning Image Decompression with Convolutional Networks
• FPGA System Design for Computer Vision with Convolutional Neural Networks
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
• Implementing Hibernation on the ARM Cortex M0
• 3D Turbo Decoder ASIC Realization
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
• ASIC Implementation of High-Throughput Next Generation Turbo Decoders
• Digital Transmitter for Mobile Communications
• FPGA-Based Digital Frontend for 3G Receivers
• Spatio-Temporal Video Filtering
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
• FFT-based Convolutional Network Accelerator
• Real-Time Optical Flow Using Neural Networks
• EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
• Synchronisation and Cyclic Prefix Handling For LTE Testbed
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
• Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
• Baseband Meets CPU
• Active-Set QP Solver on FPGA