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[[File:Sriedel_face_pulp_team.jpg|thumb|200px|]]
 
[[File:Sriedel_face_pulp_team.jpg|thumb|200px|]]
  
I finished my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2017 and 2019, respectively. Since summer 2020, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
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I finished my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2017 and 2019, respectively. Since summer 2019, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.
  
 
My main research areas are:
 
My main research areas are:

Latest revision as of 23:39, 23 January 2021

Samuel Riedel

Sriedel face pulp team.jpg

I finished my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2017 and 2019, respectively. Since summer 2019, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.

My main research areas are:

  • Computer and System Architecture
  • Manycore systems
  • Image Processing
  • Parallel Programming

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