User:Sriedel

Samuel Riedel

I finished my B.Sc. and M.Sc. in electrical engineering at ETH Zürich in 2017 and 2019, respectively. Since summer 2019, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini.

My main research areas are:

• Computer and System Architecture
• Manycore systems
• Image Processing
• Parallel Programming

Contact

• e-mail: sriedel@iis.ee.ethz.ch
• phone: +41 44 632 65 69
• office: ETZ J71.2

Projects

Available Projects

• Fast Simulation of Manycore Systems (1S)
• Ibex: Tightly-Coupled Accelerators and ISA Extensions

Projects In Progress

No pages meet these criteria.

Completed Projects

• Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
• Enabling Efficient Systolic Execution on MemPool (M)
• Running Rust on PULP
• Implementing DSP Instructions in Banshee (1S)
• Streaming Integer Extensions for Snitch (M/1-2S)
• Efficient Synchronization of Manycore Systems (M/1S)
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
• Transforming MemPool into a CGRA (M)
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• Manycore System on FPGA (M/S/G)
• ISA extensions in the Snitch Processor for Signal Processing (M)
• MemPool on HERO (1S)
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)