Difference between revisions of "User:Yiczhang"
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| − | I received my M.Sc. in electronics at Nanyang Technological University in 2017. I worked at MediaTek and Cadence | + | [[File:Yichao_Photo.jpeg||140px|thumb|right]] |
| − | Since August 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini. | + | |
| + | I received my M.Sc. in electronics at Nanyang Technological University Singapore in 2017. I have worked at MediaTek Inc. and Cadence Design System focusing on the physical design of high-performance SoCs. | ||
| + | Since August 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini | ||
| + | |||
| + | ==Research interests== | ||
| + | |||
| + | My main research interests are: | ||
| + | * Energy Efficiency Physical Design | ||
| + | * Parallel Programming | ||
| + | * Vector Processing | ||
| + | * Many-core Architecture | ||
| + | |||
| + | I work on the parallel programming of 5G physical uplink shared channel algorithm and physical implementation of MemPool and TeraPool architecture, which are two many-core architectures that have respectively 256 and 1024 cores. I am also interested in vector processing architecture (Spatz) and SIMD programming. If you are interested in one of my projects or you would like to discuss my research, please feel free to contact me by e-mail or to pass by my office! | ||
| + | |||
| + | ==Contact== | ||
| + | |||
| + | * '''Office''': OAT Building, 16th Floor, U21 | ||
| + | * '''e-mail''': [mailto:yiczhang@iis.ee.ethz.ch yiczhang@iis.ee.ethz.ch] | ||
| + | * '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.Mjg5ODc3.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Yichao Zhang (ETH page)] | ||
| + | |||
| + | ==Projects== | ||
| + | |||
| + | ===Available Projects=== | ||
| + | <DynamicPageList> | ||
| + | category = Available | ||
| + | category = Yiczhang | ||
| + | suppresserrors=true | ||
| + | ordermethod=sortkey | ||
| + | order=ascending | ||
| + | </DynamicPageList> | ||
| + | |||
| + | ===Projects In Progress=== | ||
| + | <DynamicPageList> | ||
| + | category = In progress | ||
| + | category = Yiczhang | ||
| + | </DynamicPageList> | ||
Latest revision as of 15:20, 31 October 2023
I received my M.Sc. in electronics at Nanyang Technological University Singapore in 2017. I have worked at MediaTek Inc. and Cadence Design System focusing on the physical design of high-performance SoCs. Since August 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini
Research interests
My main research interests are:
- Energy Efficiency Physical Design
- Parallel Programming
- Vector Processing
- Many-core Architecture
I work on the parallel programming of 5G physical uplink shared channel algorithm and physical implementation of MemPool and TeraPool architecture, which are two many-core architectures that have respectively 256 and 1024 cores. I am also interested in vector processing architecture (Spatz) and SIMD programming. If you are interested in one of my projects or you would like to discuss my research, please feel free to contact me by e-mail or to pass by my office!
Contact
- Office: OAT Building, 16th Floor, U21
- e-mail: yiczhang@iis.ee.ethz.ch
- www: Yichao Zhang (ETH page)
Projects
Available Projects
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
