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I received my M.Sc. in electronics at Nanyang Technological University in 2017. I worked at MediaTek and Cadence and focused on the physical design of high-performance SoCs.
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[[File:Yichao_Photo.jpeg||140px|thumb|right]]
Since August 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini. [[File:Yichao_Photo.jpeg]]
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I received my M.Sc. in electronics at Nanyang Technological University in 2017. I have worked at MediaTek and Cadence and focused on the physical design of high-performance SoCs.
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Since August 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini
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==Research interests==
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My main research interests are:
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* Energy Efficiency Physical Design
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* Parallel Programming
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* Vector Processing
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* Manycore Architecture
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I work on the parallel programming of 5G physical uplink shared channel algorithm and physical implementation of MemPool and TeraPool architecture, two manycore architectures that have respectively 256 and 1024 cores. I am also interested in vector processing architecture and SIMD programming. If you are interested in one of my projects or you would like to discuss my research, please feel free to contact me by e-mail or to pass by my office!
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==Contact==
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* '''Office''': ETZ J76.2
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* '''e-mail''': [mailto:yiczhang@iis.ee.ethz.ch yiczhang@iis.ee.ethz.ch]
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* '''www''': [https://ee.ethz.ch/the-department/people-a-z/person-detail.Mjg5ODc3.TGlzdC8zMjc5LC0xNjUwNTg5ODIw.html Yichao Zhang (ETH page)]
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==Projects==
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===Available Projects===
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<DynamicPageList>
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category = Available
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category = Yiczhang
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suppresserrors=true
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ordermethod=sortkey
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order=ascending
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</DynamicPageList>
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===Projects In Progress===
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<DynamicPageList>
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category = In progress
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category = Yiczhang
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</DynamicPageList>

Revision as of 10:35, 9 November 2022

Yichao Photo.jpeg

I received my M.Sc. in electronics at Nanyang Technological University in 2017. I have worked at MediaTek and Cadence and focused on the physical design of high-performance SoCs. Since August 2021, I am pursuing a Ph.D. in the Circuits and Systems group of Prof. Luca Benini

Research interests

My main research interests are:

  • Energy Efficiency Physical Design
  • Parallel Programming
  • Vector Processing
  • Manycore Architecture

I work on the parallel programming of 5G physical uplink shared channel algorithm and physical implementation of MemPool and TeraPool architecture, two manycore architectures that have respectively 256 and 1024 cores. I am also interested in vector processing architecture and SIMD programming. If you are interested in one of my projects or you would like to discuss my research, please feel free to contact me by e-mail or to pass by my office!

Contact

Projects

Available Projects


Projects In Progress