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VLSI Design of an Asynchronous LDPC Decoder

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Left: Factor graph describing a simple LDPC code; middle: dataflow of asynchronous VLSI designs; right: automatically-generated layout of a simple processor implemented using ACT and fabricated in 65nm CMOS.

Short Description

Virtually all modern digital VLSI designs are synchronous due to the availability of easy-to-use electronic design automation (EDA) software that significantly facilitates circuit design. The main drawback of synchronous designs, however, is the fact that the worst propagation delay (the critical path) determines the global operation frequency, whereas large parts of most designs could run at significantly faster rates. In stark contrast, asynchronous digital VLSI circuits do not rely on a global clock and enable one to operate each part of a design at the fastest possible rate. This design paradigm either enables significantly higher throughput or reduced power consumption compared to synchronous circuits. While asynchronous logic has blatant advantages over synchronous designs, asynchronous VLSI design was, up until now, not supported by EDA tools and, hence, enjoyed only limited use in practice.

The goal of this project is to use a recently developed open-source EDA tool-flow for asynchronous VLSI design developed at Yale University [1], in order to design, implement, and fabricate a low-density parity check (LDPC) decoder for fifth-generation (5G) wireless communication systems. The project will proceed in three stages: First, the student(s) will modify conventional, synchronous message-passing algorithms for LDPC decoding to enable asynchronous message passing. Second, the student(s) will design and implement the asynchronous decoding algorithm using the open-source EDA tools available at [2]. Third, the student(s) will compare their asynchronous design to state-of-the-art synchronous LDPC decoders in the same process technology.

In order to facilitate VLSI design with these experimental EDA tools [2,3], called ACT (short for Asynchronous Circuit Toolkit), the project will be co-advised by the Yale Asynchronous VLSI and Architecture Group led by Prof. Rajit Manohar.

[1] S. Ataei et al., “An Open-Source EDA Flow for Asynchronous Logic,” IEEE Design & Test, Vol. 38, No. 2, Apr. 2021

[2] https://github.com/asyncvlsi/

[3] https://avlsi.csl.yale.edu/act/doku.php

Status: Available

Looking for 1-2 Semester/Bachelor/Master students
Contact: Christoph Studer

Prerequisites

Communication Systems (or a similar course)
VLSI I (optional)

Character

50% Algorithm development
50% Asynchronous VLSI Design

Professor

Christoph Studer

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