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Information for "VLSI Implementation of a 5G Ciphering Accelerator"

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Display titleVLSI Implementation of a 5G Ciphering Accelerator
Default sort keyVLSI Implementation of a 5G Ciphering Accelerator
Page length (in bytes)3,312
Page ID1387
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page0
Counted as a content pageYes

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Page creatorMkorb (talk | contribs)
Date of page creation13:05, 13 November 2020
Latest editorMkorb (talk | contribs)
Date of latest edit09:05, 9 February 2021
Total number of edits6
Total number of distinct authors2
Recent number of edits (within past 90 days)0
Recent number of distinct authors0