Information for "VLSI Implementation of a 5G Ciphering Accelerator"
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Basic information
Display title | VLSI Implementation of a 5G Ciphering Accelerator |
Default sort key | VLSI Implementation of a 5G Ciphering Accelerator |
Page length (in bytes) | 3,312 |
Page ID | 1387 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 0 |
Counted as a content page | Yes |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | Mkorb (talk | contribs) |
Date of page creation | 13:05, 13 November 2020 |
Latest editor | Mkorb (talk | contribs) |
Date of latest edit | 09:05, 9 February 2021 |
Total number of edits | 6 |
Total number of distinct authors | 2 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |