Difference between revisions of "VLSI Implementation of a 5G Ciphering Accelerator"
From iis-projects
(2 intermediate revisions by 2 users not shown) | |||
Line 1: | Line 1: | ||
[[File:5G-Security.jpg|thumb|400px|5G Security, Source: https://5g.security]] | [[File:5G-Security.jpg|thumb|400px|5G Security, Source: https://5g.security]] | ||
==Short Description== | ==Short Description== | ||
− | + | The Internet-of-Things promising to connect everything will enable many new applications in the realm of smart homes, smart cities, industry 4.0, or smart transportation just to name a few. Quite a few of these applications including cyber-physical systems and self-driving cars demand for reliable and secure communication links in order to avoid dangerous malfunctions or external attacks. 5G cellular networks counteract these challenges by standardizing an Ultra-Reliable Low-Latency Communication (URLLC) link using strong ciphering algorithms such as AES-128 and ZUC. | |
− | + | The goal of this project is to design an hardware-efficient ASIC supporting 5G ciphering algorithms for URLLC applications. After an initial phase focusing on the familiarization with ciphering algorithms, you will develop an efficient ciphering architecture meeting the low-latency demands for URLLC. In a second part of the project, the accelerator architecture will be ported to HDL and an ASIC implementation will be derived by logic synthesis of the developed RTL code followed by a place-and-route tool flow. The work concludes with a comparison of the generated ASIC with state of the art. | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
===Status: Available === | ===Status: Available === | ||
Line 61: | Line 55: | ||
[[Category:Telecommunications]] | [[Category:Telecommunications]] | ||
[[Category:Mkorb]] | [[Category:Mkorb]] | ||
+ | [[Category:2020]] | ||
<!-- | <!-- |
Latest revision as of 10:05, 9 February 2021
Short Description
The Internet-of-Things promising to connect everything will enable many new applications in the realm of smart homes, smart cities, industry 4.0, or smart transportation just to name a few. Quite a few of these applications including cyber-physical systems and self-driving cars demand for reliable and secure communication links in order to avoid dangerous malfunctions or external attacks. 5G cellular networks counteract these challenges by standardizing an Ultra-Reliable Low-Latency Communication (URLLC) link using strong ciphering algorithms such as AES-128 and ZUC.
The goal of this project is to design an hardware-efficient ASIC supporting 5G ciphering algorithms for URLLC applications. After an initial phase focusing on the familiarization with ciphering algorithms, you will develop an efficient ciphering architecture meeting the low-latency demands for URLLC. In a second part of the project, the accelerator architecture will be ported to HDL and an ASIC implementation will be derived by logic synthesis of the developed RTL code followed by a place-and-route tool flow. The work concludes with a comparison of the generated ASIC with state of the art.
Status: Available
- Looking for Interested Master Students (Semester Project / Master Thesis)
- Contact: Matthias Korb
Prerequisites
- VLSI I
Character
- 20% Theory, Algorithms, and Simulation
- 40% Architectural Design
- 40% HDL Implementation