VLSI Implementation of a 5G Ciphering Accelerator
Today, Turbo Decoder and LDPC Decoder are well established in the majority of communication systems. While the physical baseband computation in the cellular LTE standard bases for example on Turbo codes, LDPC codes have been adopted in the WiFi standard IEEE802.11n/ac/ax. With that the question arises: What comes next?
There are various channel decoding algorithms which could potentially succeed Turbo and LDPC codes. Promising candidates are: Non-binary LDPC codes, Spatially-Coupled LDPC Codes, and Polar Codes. The goal of this project is to do a quantitative evaluation of the channel decoding candidates based on optimized VLSI implementations.
Your first task in this project will be to develop a hardware-friendly decoder architecture for one of the channel decoder candidates. After porting the decoder architecture to HDL, an ASIC implementation will be derived by logic synthesis of the developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decoder candidates.
In case a Master Thesis is pursued, one further task will be to optimize the selected fix-point decoding algorithm towards a VLSI implementation.
- Looking for Interested Master Students (Semester Project / Master Thesis)
- Contact: Matthias Korb
- VLSI I
- 20% Theory, Algorithms, and Simulation
- 40% Architectural Design
- 40% HDL Implementation