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Difference between revisions of "VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE"

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[[File:channel_shortening.png|frame]]
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[[File:channel_shortening.png|thumb]]
  
 
==Short Description==
 
==Short Description==
Today's wireless devices have to deal with multi-path propagation caused by reflecting objects along the receive paths. These reflections lead to a long channel impulse responses, which makes the channel equalization complex. Therefore channel shortening filters are used to transform the long channel impulse response into a shorter one. At IIS during the last years, several channel shortening algorithms and implementations have been presented.
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Today's wireless devices have to deal with multi-path propagation caused by reflecting objects along the receive paths. These reflections lead to a long channel impulse response, which makes the channel equalization complex. Therefore channel shortening filters are used to transform the long channel impulse response into a shorter one. At IIS during the last years, several channel shortening algorithms and implementations have been presented.
  
Your task in this project is to design and implement a hardware architecture of a novel channel shortening algorithm we developed recently [1]. You will get a MATLAB implementation of the algorithm as a reference implementation, from which you can start building your architecture. After you sketched a block diagram, you will implement the architecture in VHDL. To this end you will port the implementation to an FPGA and analyze resource utilization, or synthesize it for an ASIC implementation, depending if you want to do a semester or a Master project.
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Your task in this project is to design and implement a hardware architecture of a novel channel shortening algorithm we developed recently [1]. You will get a MATLAB implementation of the algorithm as a reference implementation, from which you can start building your architecture. After you sketched a block diagram, you will implement the architecture in HDL. Synthesis and Place&Route using CAD tool lead to an ASIC implementation.
  
===Status: Available ===
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===Status: In Progress ===
: Looking for interested students (Semester or Master Thesis)
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: Students: Robert Balas and Georg Rütishauser (sem16h7)
: Supervision: [[:User:kroell|Harald Kröll]], [[:User:Weberbe|Benjamin Weber]]
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: Supervision: [[:User:Weberbe|Benjamin Weber]], [[:User:Mkorb|Matthias Korb]]
  
 
===Character===
 
===Character===
 
: 30% Theory/Matlab
 
: 30% Theory/Matlab
: 70% VHDL
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: 70% HDL, Synthesis, Place&Route
  
 
===Prerequisites===
 
===Prerequisites===
 
: VLSI I
 
: VLSI I
: Matlab, VHDL
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: Matlab
  
 
===Professor===
 
===Professor===
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==References==  
 
==References==  
  
[1] http://www.iis.ee.ethz.ch/~kroell/papers/Ungerboeck_CS.pdf
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[1] Hu, Sha, et al. "A Low-complexity Channel Shortening Receiver with Diversity Support for Evolved 2G Devices." ''IEEE International Conference on Communications''. 2016.
  
 
[[Category:Digital]]
 
[[Category:Digital]]
[[Category:Master Thesis]]
 
 
[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
[[Category:Available]]
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[[Category:In progress]]
[[Category:FPGA]]
 
 
[[Category:ASIC]]
 
[[Category:ASIC]]
 
[[Category:Telecommunications]]
 
[[Category:Telecommunications]]
 
[[Category:Weberbe]]
 
[[Category:Weberbe]]
[[Category:Kroell]]
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[[Category:Mkorb]]

Revision as of 13:34, 19 September 2016

Channel shortening.png

Short Description

Today's wireless devices have to deal with multi-path propagation caused by reflecting objects along the receive paths. These reflections lead to a long channel impulse response, which makes the channel equalization complex. Therefore channel shortening filters are used to transform the long channel impulse response into a shorter one. At IIS during the last years, several channel shortening algorithms and implementations have been presented.

Your task in this project is to design and implement a hardware architecture of a novel channel shortening algorithm we developed recently [1]. You will get a MATLAB implementation of the algorithm as a reference implementation, from which you can start building your architecture. After you sketched a block diagram, you will implement the architecture in HDL. Synthesis and Place&Route using CAD tool lead to an ASIC implementation.

Status: In Progress

Students: Robert Balas and Georg Rütishauser (sem16h7)
Supervision: Benjamin Weber, Matthias Korb

Character

30% Theory/Matlab
70% HDL, Synthesis, Place&Route

Prerequisites

VLSI I
Matlab

Professor

Qiuting Huang

References

[1] Hu, Sha, et al. "A Low-complexity Channel Shortening Receiver with Diversity Support for Evolved 2G Devices." IEEE International Conference on Communications. 2016.