# Difference between revisions of "WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing"

### From iis-projects

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− | == | + | ==Abstract== |

− | + | This thesis proposes a complete cell-search solution for real-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an inaccuracy of crystal oscillators within handsets and could cause fatal performance degradation. | |

− | + | A pipelined process of the code and time synchronization algorithm that minimizes the average code acquisition time, while keeping the complexity to a minimum, is considered. The effect of the frequency error (which may be as large as 30 kHz) on the initial cell search is marginalized by partial symbol despreading and non-coherent combining. Furthermore a coarse frequency | |

− | + | estimation step where residual frequency error is reduced to a configurable amount (1 kHz is our value of choice) is implemented. Then a fine frequency estimation and tracking algorithm is designed utilizing a mapping of the closed form solution of the exponential sum problem within a closed-loop. This ensures a fine residual frequency offset less than 50 Hz. | |

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− | + | A series of fixed point simulations were conducted to minimize the circuit complexity. Further optimizations are considered in the design of hardware architecture and circuits to reduce the area and power consumption. The Digital Front End (DFE) is integrated with a Time Processing Unit (TPU) and a CPU along with the control logic to implement the digital part of a modem SoC. The entire DFE occupies a core area of 0.62 mm2 in a 1.2-V 0.13-μm CMOS technology with clock rate 76.8 MHz. Finally, to verify and demonstrate the cell search procedures, the developed modem is mapped to a Kintex 7 FPGA in conjunction with a commercial RF from ACP AG. | |

− | ===Status: | + | ===Status: Completed === |

: Student: Taimir Aguacil (msc16f15) | : Student: Taimir Aguacil (msc16f15) | ||

: Supervision: [[:User:Weberbe|Benjamin Weber]], [[:User:Mkorb|Matthias Korb]], [[:User:Msalomon|Mauro Salomon]] | : Supervision: [[:User:Weberbe|Benjamin Weber]], [[:User:Mkorb|Matthias Korb]], [[:User:Msalomon|Mauro Salomon]] | ||

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===Professor=== | ===Professor=== | ||

: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] | : [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang] | ||

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[[Category:Digital]] | [[Category:Digital]] | ||

− | [[Category: | + | [[Category:Completed]] |

[[Category:Master Thesis]] | [[Category:Master Thesis]] | ||

[[Category:FPGA]] | [[Category:FPGA]] |

## Revision as of 15:36, 1 December 2016

## Abstract

This thesis proposes a complete cell-search solution for real-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an inaccuracy of crystal oscillators within handsets and could cause fatal performance degradation.

A pipelined process of the code and time synchronization algorithm that minimizes the average code acquisition time, while keeping the complexity to a minimum, is considered. The effect of the frequency error (which may be as large as 30 kHz) on the initial cell search is marginalized by partial symbol despreading and non-coherent combining. Furthermore a coarse frequency estimation step where residual frequency error is reduced to a configurable amount (1 kHz is our value of choice) is implemented. Then a fine frequency estimation and tracking algorithm is designed utilizing a mapping of the closed form solution of the exponential sum problem within a closed-loop. This ensures a fine residual frequency offset less than 50 Hz.

A series of fixed point simulations were conducted to minimize the circuit complexity. Further optimizations are considered in the design of hardware architecture and circuits to reduce the area and power consumption. The Digital Front End (DFE) is integrated with a Time Processing Unit (TPU) and a CPU along with the control logic to implement the digital part of a modem SoC. The entire DFE occupies a core area of 0.62 mm2 in a 1.2-V 0.13-μm CMOS technology with clock rate 76.8 MHz. Finally, to verify and demonstrate the cell search procedures, the developed modem is mapped to a Kintex 7 FPGA in conjunction with a commercial RF from ACP AG.

### Status: Completed

- Student: Taimir Aguacil (msc16f15)
- Supervision: Benjamin Weber, Matthias Korb, Mauro Salomon