Difference between revisions of "WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing"
(Created page with "thumb|Aspired testbed setup with L2/L3 processing on [[PULP as well as dedicated DBB processing on an FPGA and RF on evaLTE FMC module. ]] ==Introduc...")
m (Weberbe moved page WCDMA/HSPA+ Modem System Design, Implementation, and Testing to WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing: new project title)
Revision as of 15:33, 1 December 2016
Mobile communication modems face the ever increasing challenge of multi-mode support. The times when a 2G cellular modem was a success are long past. Today, only SoCs with 2G/3G/4G, WiFi, and Bluetooth support seem to have a right to exist in the smart phone industry. On the other hand, power consumption requirements are ever more stringent and are hard to fulfill with simultaneous multi-mode support. One option to cope with this problem is the use of dedicated VLSI IP cores, one for each standard, in a complete SoC. During this project, the base for a 3G UMTS baseband core shall be laid.
The overall goal of this project is to implement a 3G UMTS/HSPA+ modem in VLSI by reusing building blocks from other projects whenever possible. The Figure illustrates the modem setup consisting of
- RF: up/down conversion, ADC/DAC, connect using RBDP  to signal processing blocks
- Digital Baseband Processing (DBB): synchronization, equalization, (de)modulation, channel (de)coding, connects to RF via data plane of RBDP
- Time Processing Unit (TPU): timing sensitive control of DBB, RF, and Power Amplifier (PA) via events and sequences, connects to RF via control plane of RBDP
- CPU: protocol stack software on top of a Real Time OS (RTOS), peripheral interconnect
Only the blue shaded part of the Figure shall be implemented during this project. This excludes peripherals such as SIM, Audio, and so on. As the implementation of the DBB would exceed the scope of a Master thesis only the cell search procedure shall be implemented. Furthermore, only rudimentary protocol stack software shall be written, just enough to hold a demonstration. The resulting system shall be demonstrated on an FPGA based testbed for fast prototyping and verification. A commercial RF hosted on the evaLTE FMC module provides analog functions.
Status: In Progress
 Radio Front End - Baseband Digital Parallel (RBDP) Interface. https://www.jedec.org/standards-documents/docs/jesd-207, March 2007.