Zephyr RTOS on PULP
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
Real-time systems are systems that need to guarantee certain time constraints such as for example responding within a certain time frame. This means that computations not only need to be logically correct but also the physical instant of the result computation has to meet a particular timing constraint.
Regular general-purpose operating systems such as Linux are often not designed to ensure that real-time constraints are respected.
To address that problem several so called real-time operating systems have been developed in the last decades and used in several fields where the design of safety-critical systems matters (automotive and aerospace above all). Among these, Zephyr OS  is a promising scalable real-time operating system with small memory footprint designed for resource-constrained systems following modern security practices. It supports a lot of architectures such as ARM (Cortex series), MIPS, SPARC, AMD64, and RISC-V. The development model is very similar to the linux kernel: The kernel sources, drivers and any bootstrapping code are part of the same project giving a nice out-of-the-box experience.
ControlPULP is an open-source HW/SW platform based on PULP , a parallel embedded MCU implementing the RISC-V ISA. ControlPULP has been developed to serve as an integrated power controller for HPC processors . In this scenario, a timely response from multiple MIMO interfaces is required to be able to track and set the operating point of the controlled system in a workload-aware manner.
Currently, we already support FreeRTOS  in ControlPULP as real-time operating system
The goal of this project is to port Zephyr OS to ControlPULP:
- Review and study ControlPULP SystemVerilog code 
- (Optional) If you prefer to develop on an FPGA set up the ControlPULP FPGA flow
- Review and study ZephyrOS. You can have a look how previous ports were done 
- Port the kernel and interrupt drivers to support ControlPULP
- Add drivers for various peripherals (UART, SPI, I2C, ...)
- Do various comparisons against FreeRTOS
- 15% Literature / architecture review
- 65% Software layer
- 20% Evaluation
- Experience with digital design in SystemVerilog as taught in VLSI I
- Basic knowledge of operating systems
- Knowledge of C programming language and unix tooling as from previous bachelor/master courses
 ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration