Low-power chip-to-chip communication network
One of the challenges of IC design is providing sufficient I/O bandwidth. This is even harder for smaller chips (like the ones relevant for our research) as there are usually not enough number of I/O pins to take advantage of parallelization. Most solutions center on fast serial communications.
In this work, we will assume that we have already an efficient serial interface (this is the topic of other ongoing projects). What we want is a way to connect two chips running PULP (or PULPino) systems over this fast serial interface so that they can exchange data with the minimum amount of energy consumption. There are several practical solutions from both academia and industry. Your job will be to investigate these methods, use/adapt/modify existing techniques or come up with a new method, add the necessary interface that will allow data to be transferred between two PULP chips, develop the HDL code for both the receiver and transmitter and make it work. The system should be an IP that seamlessly attaches to the PULP system. The final goal would be to add such an interface to an existing PULP system and tape it out as an ASIC. If successful, this will form the standard chip to chip communication standard for the PULP system.
- Looking for 1-2 Semester/Master students
- Contact: Frank K. Gurkaynak
- VLSI I
- VLSI II (recommended)
- 40% Theory
- 40% HDL Design
- 20% ASIC Design
Detailed Task Description
- Adapteva low latency chip to chip interface
- BaseJump.org The UCSD BGA package and libraries from group of Prof. Michael Taylor